IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 127

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: IP Core Interfaces
Avalon-ST Interface
Table 5–20. Power Management Signals
Table 5–21. Power Management Capabilities Register
Table 5–22. Power Management Capabilities Register Field Descriptions (Part 1 of 2)
December 2010 Altera Corporation
pm_event
pm_data[9:0]
pm_auxpwr
3124
[31:24]
[22:16]
[15]
[14:13]
register
Bits
data
Signal
Data register
reserved
PME_status
data_scale
2216
rsvd
Field
Table 5–21
Table 5–22
Capabilities register.
I/O
I
I
I
PME_status
Power Management Event. This signal is only available in the hard IP End Point
implementation.
Endpoint—initiates a a power_management_event message (PM_PME) that is sent to the
root port. If the IP core is in a low power state, the link exists from the low-power state to
send the message. This signal is positive edge-sensitive.
Power Management Data. This signal is only available in the hard IP implementation.
This bus indicates power consumption of the component. This bus can only be
implemented if all three bits of AUX_power (part of the Power Management Capabilities
structure) are set to 0. This bus includes the following bits:
■
■
For example, the two registers might have the following values:
■
■
To find the maximum power consumed by this component, multiply the data value by the
data Scale (114 × .01 = 1.14). 1.14 watts is the maximum power allocated to this
component in the power state selected by the data_select field.
Power Management Auxiliary Power: This signal is only available in the hard IP
implementation. This signal can be tied to 0 because the L2 power state is not supported.
15
pm_data[9:2]: Data Register: This register is used to maintain a value associated with
the power consumed by the component. (Refer to the example below)
pm_data[1:0]: Data Scale: This register is used to maintain the scale used to find the
power consumed by a particular component and can include the following values:
b’00: unknown
b’01: 0.1 ×
b’10: 0.01 ×
b’11: 0.001 ×
pm_data[9:2]: b’1110010 = 114
pm_data[1:0]: b’10, which encodes a factor of 0.01
This field indicates in which power states a function can assert the PME# message.
When this signal is set to 1, it indicates that the function would normally assert the PME#
message independently of the state of the PME_en bit.
This field indicates the scaling factor when interpreting the value retrieved from the data
register. This field is read-only.
shows the layout of the Power Management Capabilities register.
outlines the use of the various fields of the Power Management
1413
data_scale
129
data_select
Description
Description
—
PME_EN
8
PCI Express Compiler User Guide
72
rsvd
10
PM_state
5–43