IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 339

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter :
Recommended Incremental Compilation Flow
Table B–15. Application-Side TX Signals
Recommended Incremental Compilation Flow
December 2010 Altera Corporation
tx_st_valid0
tx_st_data0
tx_st_ready0
tx_stream_cred0
tx_stream_mask0
Signal
f
TX Ports
Table B–15
When using the incremental compilation flow, Altera recommends that you include a
fully registered boundary on your application. By registering signals, you reserve the
entire timing budget between the application and PCI Express IP core for routing.
Refer to
volume 1 of the Quartus II Handbook.
The following is a suggested incremental compile flow. The instructions cover
incremental compilation for both the Avalon-ST and the descriptor/data interfaces.
63:0
71:64
72
73
74
65:0
Bit
Quartus II Incremental Compilation for Hierarchical and Team-Based Design
tx_desc/tx_data
tx_eop_flag
tx_sop_flag
tx_err
describes the application-side TX signals.
Subsignals
Avalon-ST TX Interface Signals
Other TX Interface Signals
Clocks tx_st_data0 into the ICM. The ICM accepts data when
tx_st_valid0 is high.
Multiplexed tx_desc0/tx_data0 bus.
Refer to for information on
tx_data0.
Unused bits
Asserts on the last cycle of the packet
Asserts on the 1st cycle of the packet
Same as IP core definition. Refer to
information.
The ICM asserts this signal when it can accept more data. The ICM
deasserts this signal to throttle the data. When the ICM deasserts this
signal, the user application must also deassert tx_st_valid0 within
3 clk cycles.
Available credits in IP core (credit limit minus credits consumed).
This signal corresponds to tx_cred0 from the PCI Express IP core
delayed by one system clock cycle. This information can be used by
the application to send packets based on available credits. Note that
this signal does not account for credits consumed in the ICM. Refer to
Table B–8 on page B–15
Asserted by ICM to throttle Non-Posted requests from application.
When set, application should stop issuing Non-Posted requests in
order to prevent head-of-line blocking.
1st cycle – tx_desc0[127:64]
2nd cycle – tx_desc0[63:0]
3rd cycle – tx_data0 (if any)
for information on tx_cred0.
Table B–6 on page B–12
Description
Table B–8 on page B–15
PCI Express Compiler User Guide
tx_desc0 and
for more
in
B–33