IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 51

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 3: Parameter Settings
Capabilities Parameters
Table 3–3. Capabilities Parameters (Part 3 of 4)
December 2010 Altera Corporation
Link common clock
Data link layer active
reporting
0x094
Surprise down
reporting
Link port number
Enable slot
capability
Slot capability
register
Implement MSI-X
MSI-X Table size
0x068[26:16]
MSI-X Table
Offset
MSI-X Table BAR
Indicator
BIR
Parameter
On/Off
On/Off
On/Off
0x01
On/Off
0x00000000
On/Off
10:0
31:3
<5–1>:0
Value
Electromechanical Interlock Present
31
Indicates if the common reference clock supplied by the system is used as the
reference clock for the PHY. This parameter sets the read-only value of the slot clock
configuration bit in the link status register.
Turn this option on for a downstream port if the component supports the optional
capability of reporting the DL_Active state of the Data Link Control and Management
State Machine. For a hot-plug capable downstream port (as indicated by the Hot-
Plug Capable field of the Slot Capabilities register), this option must be
turned on. For upstream ports and components that do not support this optional
capability, turn this option off.
When this option is on, a downstream port supports the optional capability of
detecting and reporting the surprise down error condition.
Sets the read-only values of the port number field in the link capabilities register.
The slot capability is required for root ports if a slot is implemented on the port. Slot
status is recorded in the PCI Express Capabilities register. Only valid for root
port variants.
Defines the characteristics of the slot. You turn this option on by selecting Enable
slot capability. The various bits are defined as follows:
The MSI-X functionality is only available in the hard IP implementation.
System software reads this field to determine the MSI-X Table size <N>, which is
encoded as <N–1>. For example, a returned value of 10’b00000000011 indicates a
table size of 4. This field is read-only.
Points to the base of the MSI-X Table. The lower 3 bits of the Table BIR are set to
zero by software to form a 32-bit qword-aligned offset. This field is read-only.
Indicates which one of a function’s Base Address registers, located beginning at
0x10 in configuration space, is used to map the MSI-X table into memory space.
This field is read-only. Depending on BAR settings, from 2 to BARs are available.
No Command Completed Support
MSI-X Capabilities (0x68, 0x6C, 0x70)
Physical Slot Number
Attention Indicator Present
Power Controller Present
Attention Button Present
Power Indicator Present
Slot Power Limit Scale
Slot Power Limit Value
MRL Sensor Present
Hot-Plug Surprise
Hot-Plug Capable
Link Capabilities
Slot Capabilities
0x090
0x094
19 18 17 16 15 14
Description
7 6 5
PCI Express Compiler User Guide
4 3
2 1
0
3–9