IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 148

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

6–4
Table 6–5. MSI-X Capability Structure, Rev2 Spec: MSI and MSI-X Capability Structures
Table 6–6. Power Management Capability Structure, Rev2 Spec: Power Management Capability Structure
Table 6–7. PCI Express Capability Structure Version 1.0a and 1.1
Register and PCI Express Capability List Register
PCI Express Compiler User Guide
0x068
0x06C
Note to
(1) Refer to
0x078
0x07C
Note to
(1) Refer to
0x080
0x084
0x088
0x08C
0x090
0x094
0x098
0x09C
0x0A0
Note to
(1) Reserved and preserved. As per the PCI Express Base Specification 1.1, this register is reserved for future RW implementations. Registers are
(2) Refer to
Base Specification 2.0.
Base Specification 2.0.
read-only and must return 0 when read. Software must preserve the value read for writes to bits.
Base Specification 2.0.
Byte Offset
Byte Offset
Byte Offset
Table
Table
Table
Table 6–23 on page 6–12
Table 6–23 on page 6–12
Table 6–23 on page 6–12
6–5:
6–6:
6–7:
Table 6–5
Table 6–6
Table 6–7
and 1.1.
Capabilities Register
Data
PCI Express Capabilities Register
for a comprehensive list of correspondences between the configuration space registers and the
for a comprehensive list of correspondences between the configuration space registers and the
for a comprehensive list of correspondences between the configuration space registers and the
31:24
31:24
31:24
describes the MSI-X capability structure.
describes the power management capability structure.
describes the PCI Express capability structure for specification versions 1.0a
MSI-X Table
Message Control
Device Status
Link Status
Slot Status
Reserved
size[26:16]
PM Control/Status
Bridge Extensions
MSI-X Table Offset
23:16
23:16
23:16
Device Capabilities
Link Capabilities
Slot Capabilities
Root Status
(Note
Next Cap PTR
Power Management Status & Control
1), Rev2 Spec: PCI Express Capabilities
Next Cap Pointer
Next Cap Ptr
15:8
15:8
15:8
Device Control
Configuration Space Register Content
Root Control
December 2010 Altera Corporation
Link Control
Slot Control
Chapter 6: Register Descriptions
Cap ID
PCI Express Cap ID
Capability ID
7:3
7:0
7:0
PCI Express
PCI Express
PCI Express
BIR
2:0