IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 156

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

6–12
Table 6–21. Avalon-MM-to-PCI Express Mailbox Registers, Read/Write (Part 2 of 2)
Table 6–22. PCI Express-to-Avalon-MM Mailbox Registers, Read-Only
Comprehensive Correspondence between Config Space Registers and
PCIe Spec Rev 2.0
Table 6–23. Correspondence Configuration Space Registers and PCI Express Base Specification Rev. 2.0 Description
PCI Express Compiler User Guide
0x3A08
0x3A0C
0x3A10
0x3A14
0x3A18
0x3A1C
0x3B00
0x3B04
0x3B08
0x3B0C
0x3B10
0x3B14
0x3B18
0x3B1C
Byte Address
0x000:0x03C
0x000:0x03C
0x040:0x04C
0x050:0x05C
0x068:0x070
0x070:0x074
0x078:0x07C
0x080:0x0B8
0x080:0x0B8
Address
Address
A2P _MAILBOX2
A2P _MAILBOX3
A2P _MAILBOX4
A2P _MAILBOX5
A2P _MAILBOX6
A2P_MAILBOX7
P2A_MAILBOX0
P2A_MAILBOX1
P2A_MAILBOX2
P2A_MAILBOX3
P2A_MAILBOX4
P2A_MAILBOX5
P2A_MAILBOX6
P2A_MAILBOX7
Config Reg Offset 31:24 23:16 15:8 7:0
PCI Header Type 0 configuration registers
PCI Header Type 1 configuration registers
Reserved
MSI capability structure
MSI capability structure
Reserved
Power management capability structure
PCI Express capability structure
PCI Express capability structure
Name
Name
The PCI Express-to-Avalon-MM mailbox registers are read-only at the addresses
shown in
corresponding bit in the Avalon-MM interrupt status register is set to 1.
Table 6–23
space registers and their descriptions in the
Table
provides a comprehensive correspondence between the configuration
Table 6-1.
Access
Access
Mode
6–22. The Avalon-MM processor reads these registers when the
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
Common Configuration Space Header
Comprehensive Correspondence between Config Space Registers and PCIe Spec Rev 2.0
Avalon-MM-to-PCI Express mailbox 2
Avalon-MM-to-PCI Express mailbox 3
Avalon-MM-to-PCI Express mailbox 4
Avalon-MM-to-PCI Express mailbox 5
Avalon-MM-to-PCI Express mailbox 6
Avalon-MM-to-PCI Express mailbox 7
PCI Express-to-Avalon-MM mailbox 0.
PCI Express-to-Avalon-MM mailbox 1
PCI Express-to-Avalon-MM mailbox 2
PCI Express-to-Avalon-MM mailbox 3
PCI Express-to-Avalon-MM mailbox 4
PCI Express-to-Avalon-MM mailbox 5
PCI Express-to-Avalon-MM mailbox 6
PCI Express-to-Avalon-MM mailbox 7
Corresponding Section in PCIe Specification
Type 0 Configuration Space Header
Type 1 Configuration Space Header
MSI and MSI-X Capability Structures
MSI and MSI-X Capability Structures
PCI Power Management Capability Structure
PCI Express Capability Structure
PCI Express Capability Structure
PCI Express Base Specification 2.0.
Description
Description
Address Range: 0x3800-0x3B1F
Address Range: 0x3A00-0x3A1F
December 2010 Altera Corporation
Chapter 6: Register Descriptions