IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 263

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 15: Testbench and Design Example
BFM Procedures and Functions
Table 15–23. ebfm_barwr Procedure
Table 15–24. ebfm_barwr_imm Procedure
December 2010 Altera Corporation
Location
Syntax
Arguments
Location
Syntax
Arguments
ebfm_barwr(bar_table, bar_num, pcie_offset, lcladdr, byte_len, tclass)
bar_table
bar_num
pcie_offset
lcladdr
byte_len
tclass
ebfm_barwr_imm(bar_table, bar_num, pcie_offset, imm_data, byte_len, tclass)
bar_table
bar_num
pcie_offset
imm_data
byte_len
tclass
altpcietb_bfm_rdwr.v or altpcietb_bfm_rdwr.vhd
altpcietb_bfm_rdwr.v or altpcietb_bfm_rdwr.vhd
ebfm_barwr Procedure
The ebfm_barwr procedure writes a block of data from BFM shared memory to an
offset from the specified endpoint BAR. The length can be longer than the configured
MAXIMUM_PAYLOAD_SIZE; the procedure breaks the request up into multiple
transactions as needed. This routine returns as soon as the last transaction has been
accepted by the VC interface module.
ebfm_barwr_imm Procedure
The ebfm_barwr_imm procedure writes up to four bytes of data to an offset from the
specified endpoint BAR.
structure stores the address assigned to each BAR so that the driver code does not need
to be aware of the actual assigned addresses only the application specific offsets from the
BAR.
Address of the endpoint bar_table structure in BFM shared memory. The bar_table
Number of the BAR used with pcie_offset to determine PCI Express address.
Address offset from the BAR base.
BFM shared memory address of the data to be written.
Length, in bytes, of the data written. Can be 1 to the minimum of the bytes remaining in
the BAR space or BFM shared memory.
Traffic class used for the PCI Express transaction.
Address of the endpoint bar_table structure in BFM shared memory. The bar_table
structure stores the address assigned to each BAR so that the driver code does not need
to be aware of the actual assigned addresses only the application specific offsets from
the BAR.
Number of the BAR used with pcie_offset to determine PCI Express address.
Address offset from the BAR base.
Data to be written. In VHDL, this argument is a std_logic_vector(31 downto 0). In
Verilog HDL, this argument is reg [31:0].In both languages, the bits written depend on
the length as follows:
Length Bits Written
4
3
2
1
Length of the data to be written in bytes. Maximum length is 4 bytes.
Traffic class to be used for the PCI Express transaction.
31 downto 0
23 downto 0
15 downto 0
7 downto 0
PCI Express Compiler User Guide
15–35