IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 68

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–10
Figure 4–7. Architecture of the Transaction Layer: Dedicated Receive Buffer per Virtual Channel
PCI Express Compiler User Guide
Towards Application Layer
Virtual Channel 1
Virtual Channel 0
Virtual Channel 1
Virtual Channel 0
Rx0 Data
Rx0 Descriptor
Tx1 Data
Tx1 Descriptor
Tx1 Control
Tx0 Descriptor
Tx0 Control
Rx0 Control
& Status
Rx1 Data
Rx1 Descriptor
Rx1 Control
& Status
Tx0 Data
4. The transaction layer packet FIFO block stores the address of the buffered
5. The receive sequencing and reordering block shuffles the order of waiting
transaction layer packet.
transaction layer packets as needed, fetches the address of the priority transaction
layer packet from the transaction layer packet FIFO block, and initiates the transfer
of the transaction layer packet to the application layer.
Interface Established per Virtual Channel
Rx0 Sequencing
Rx1 Sequencing
Tx1 Request
Tx0 Request
Sequencing
Sequencing
& Reordering
& Reordering
Type 0 Configuration Space
Posted & Completion
Posted & Completion
Receive Buffer
Receive Buffer
Non-Posted
Non-Posted
Flow Control Update
Check & Reordering
Check & Reordering
Flow Control Update
Transaction Layer
Transaction Layer
Flow Control
Flow Control
Packet FIFO
Packet FIFO
Interface Established per Component
Virtual Channel
Arbitration & Tx
Sequencing
Towards Data Link Layer
Tx Transaction Layer
Packet Description
& Data
Rx Flow
Control Credits
Rx Transaction
Layer Packet
Tx Flow
Control Credits
December 2010 Altera Corporation
Chapter 4: IP Core Architecture
Transmit
Data Path
Configuration
Space
Receive
Data Path
Transaction Layer