IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 57

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 3: Parameter Settings
Avalon-MM Configuration
Table 3–6. Avalon Configuration Settings (Part 2 of 2)
December 2010 Altera Corporation
Address translation table size
Fixed Address Translation Table Contents
Avalon-MM CRA port
Number of address
pages
Size of address pages
PCIe base address
Type
Parameter
1, 2, 4, 8, 16
1 MByte–2 GBytes
32-bit
64-bit
32-bit Memory
64-bit Memory
Enable
Disable
Value
Sets Avalon-MM-to-PCI Express address translation windows and size.
Specifies the number of PCI Express base address pages of memory
that the bridge can access. This value corresponds to the number of
entries in the address translation table. The Avalon address range is
segmented into one or more equal-sized pages that are individually
mapped to PCI Express addresses. Select the number and size of the
address pages. If you select a dynamic translation table, use several
address translation table entries to avoid updating a table entry before
outstanding requests complete.
Specifies the size of each PCI Express memory segment accessible by
the bridge. This value is common for all address translation entries.
Specifies the type and PCI Express base addresses of memory that the
bridge can access. The upper bits of the Avalon-MM address are
replaced with part of a specific entry. The MSBs of the Avalon-MM
address, used to index the table, select the entry to use for each
request. The values of the lower bits (as specified in the size of address
pages parameter) entered in this table are ignored. Those lower bits are
replaced by the lower bits of the incoming Avalon-MM addresses.
Allows read/write access to bridge registers from Avalon using a
specialized slave port. Disabling this option disallows read/write access
to bridge registers.
Description
PCI Express Compiler User Guide
3–15