IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 97

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: IP Core Interfaces
Avalon-ST Interface
Figure 5–14. Avalon-ST RX Interface Timing
Table 5–4. 64-, 128-, or 256-Bit Avalon-ST TX Datapath (Part 1 of 5)
December 2010 Altera Corporation
tx_st_ready<n>
tx_st_valid<n>
64-, 128-, or 256-Bit Avalon-ST TX Port
Signal
f
(1) (2)
(2)
rx_st_data[63:0]
For a complete description of the TLP packet header formats, refer to
Transaction Layer Packet (TLP) Header
Figure 5–14
core deasserts rx_st_valid in response to the deassertion of rx_st_ready from the
application.
Table 5–4
rx_st_ready
rx_st_valid
rx_st_sop
rx_st_eop
clk
describes the signals that comprise the Avalon-ST TX Datapath.
1
1
1
Width Dir
illustrates the timing of the Avalon-ST RX interface. On this interface, the
h1
2
h2
O
I
3
data0 data1 data2 data3
ready
valid
Avalon-ST
4
Type
max latency
3 cycles
5
Indicates that the PCIe core is ready to accept data for
transmission. The core deasserts this signal to throttle
the data stream. In the hard IP implementation,
tx_st_ready<n> may be asserted during reset. The
application should wait at least 2 clock cycles after the
reset is released before issuing packets on the Avalon-ST
TX interface. The reset_status signal can also be used
to monitor when the IP core has come out of reset.
When tx_st_ready<n>, tx_st_valid<n> and
tx_st_data<n> are registered (the typical case) Altera
recommends a readyLatency of 2 cycles to facilitate
timing closure; however, a readyLatency of 1 cycle is
possible.
To facilitate timing closure, Altera recommends that you
register both the tx_st_ready and tx_st_valid
signals. If no other delays are added to the ready-valid
latency, this corresponds to a readyLatency of 2.
Clocks tx_st_data<n> into the core. Between
tx_st_sop<n> and tx_st_eop<n>, must be asserted if
tx_st_ready<n> is asserted. When tx_st_ready<n>
deasserts, this signal must deassert within 1, 2, or 3
clock cycles for soft IP implementation and within 1 or 2
clock cycles for hard IP
6
Formats.
7
data4
8
9
data5 data6
Description
10
PCI Express Compiler User Guide
11
Appendix A,
5–13