IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 65

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 4: IP Core Architecture
Application Interfaces
December 2010 Altera Corporation
1
5. The application waits at least 3 more clock cycles for tx_cred to reflect the
6. Repeat from Step 2.
For Arria II GX, Arria II GZ, HardCopy IV GX, and Stratix IV GX devices, the value of
the non-posted tx_cred represents that there are at least that number of credits
available. The non-posted credits displayed may be less than what is actually
available to the core.
The Avalon-ST TX datapath has a latency range of 3 to 6 pld_clk cycles.
TX Datapath—Stratix V GX/GS
For Stratix V GX devices, the IP core provides the credit limit information as output
signals.The application layer may track credits consumed and use the credit limit
information to calculate the number of credits available. However, to enforce the PCI
Express flow control protocol the IP core also checks the available credits before
sending a request to the link, and if the application layer violates the available credits
for a TLP it transmits, the IP core blocks that TLP and all future TLPs until credits
become available. By tracking the credit consumed information and calculating the
credits available, the application layer can optimize performance by selecting for
transmission only TLPs that have credits available. Refer to
Signals for Stratix V” on page 5–16
interface.
LMI Interface (Hard IP Only)
The LMI bus provides access to the PCI Express configuration space in the transaction
layer. For more LMI details, refer to the
page
PCI Express Reconfiguration Block Interface (Hard IP Only)
The PCI Express reconfiguration bus allows you to dynamically change the read-only
values stored in the configuration registers. For detailed information refer to the
Express Reconfiguration Block Signals—Hard IP Implementation” on page
MSI (Message Signal Interrupt) Datapath
The MSI datapath contains the MSI boundary registers for incremental compilation.
The interface uses the transaction layer's request–acknowledge handshaking protocol.
You use the TX FIFO empty flag from the TX datapath FIFO for TX/MSI
synchronization. When the TX block application drives a packet to the Avalon-ST
adapter, the packet remains in the TX datapath FIFO as long as the IP core throttles
this interface. When it is necessary to send an MSI request after a specific TX packet,
you can use the TX FIFO empty flag to determine when the IP core receives the TX
packet.
consumed credits. tx_cred does not update with more credits until the current
tx_cred allocation is exhausted.
5–40.
for more information about the signals in this
“LMI Signals—Hard IP Implementation” on
“Component Specific
PCI Express Compiler User Guide
5–41.
“PCI
4–7