IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 253

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 15: Testbench and Design Example
Root Port Design Example
December 2010 Altera Corporation
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Files in subdirectory <variation_name>_example/common/testbench:
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altpcierd_tl_cfg_sample.v—accesses configuration space signals from the variant.
Refer to the
this module.
altpcietb_bfm_ep_example_chaining_pipen1b.vo—the simulation model for the
chaining DMA endpoint.
altpcietb_bfm_shmem.v, altpcietb_bfm_shmem_common.v—root port memory
space. Refer to the
module
altpcietb_bfm_rdwr.v— requests PCI Express read and writes. Refer to the
Port BFM” on page 15–26
altpcietb_bfm_configure.v— configures PCI Express configuration space
registers in the root port and endpoint. Refer to the
page 15–26
altpcietb_bfm_log.v, and altpcietb_bfm_log_common.v—displays and logs
simulation messages. Refer to the
description of this module.
altpcietb_bfm_req_intf.v, and altpcietb_bfm_req_intf_common.v—includes
tasks used to manage requests from altpcietb_bfm_rdwr to altpcietb_vc_intf_ast.
Refer to the
altpcietb_bfm_constants.v—contains global constants used by the root port BFM.
altpcietb_ltssm_mon.v—displays LTSSM state transitions.
altpcietb_pipe_phy.v, altpcietb_pipe_xtx2yrx.v, and altpcie_phasefifo.v—used to
simulate the PHY and support circuitry.
altpcie_pll_100_125.v, altpcie_pll_100_250.v, altpcie_pll_125_250.v,
altpcie_pll_phy0.v, altpcie_pll_phy1_62p5.v, altpcie_pll_phy2.v,
altpcie_pll_phy3_62p5.v, altpcie_pll_phy4_62p5.v, altpcie_pll_phy5_62p5.v—
PLLs used for simulation. The type of PHY interface selected for the variant
determines which PLL is used.
altpcie_4sgx_alt_reconfig.v—transceiver reconfiguration module used for
simulation.
altpcietb_rst_clk.v— generates PCI Express and reference clock.
for a full description of this module
“Chaining DMA Design Example” on page 15–6
“Root Port BFM” on page 15–26
“Root Port BFM” on page 15–26
for a full description of this module.
“Root Port BFM” on page 15–26
for a full description of this module.
for a full description of this
“Root Port BFM” on
PCI Express Compiler User Guide
for a description of
for a full
“Root
15–25