IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 232

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

15–4
Table 15–1. Testbench VHDL Generics /Verilog HDL Parameters
Root Port Testbench
Figure 15–2. Testbench Top-Level Module for Root Port Designs
PCI Express Compiler User Guide
PIPE_MODE_SIM
NUM_CONNECTED_LANES
FAST_COUNTERS
Testbench Top-Level
Generic/Parameter
(<variation_name>_example_rp_pipen1b)
(altpcietb_bfm_driver_rp)
Root Port BFM
Root Port DUT
The testbench has several VHDL generics/Verilog HDL parameters that control the
overall operation of the testbench. These generics are described in
The root port testbench is provided in the subdirectory <variation_name>_examples/
root_port/testbench in your project directory. The top-level testbench is named
<variation_name>_rp_testbench.
testbench.
This testbench simulates up to an ×8 PCI Express link using either the PIPE interfaces
of the root port and endpoints or the serial PCI Express interface. The testbench
design does not allow more than one PCI Express link to be simulated at a time. The
top-level of the testbench instantiates four main modules:
■
<variation name>_example_rp_pipen1b—This is the example root port design that
includes your variation of the IP core. For more information about this module,
refer to
(<variation_name>_testbench)
0 or 1
1,2,4,8
0 or 1
Allowed
“Root Port Design Example” on page
Values
Default
Value
PIPE Interconnection
1
8
1
(altpcierd_pipe_phy)
Module x8
Selects the PIPE interface (PIPE_MODE_SIM=1) or the serial
interface (PIPE_MODE_SIM= 0) for the simulation. The PIPE
interface typically simulates much faster than the serial
interface. If the variation name file only implements the PIPE
interface, then setting PIPE_MODE_SIM to 0 has no effect and
the PIPE interface is always used.
Controls how many lanes are interconnected by the testbench.
Setting this generic value to a lower number simulates the
endpoint operating on a narrower PCI Express interface than
the maximum.
If your variation only implements the ×1 IP core, then this
setting has no effect and only one lane is used.
Setting this parameter to a 1 speeds up simulation by making
many of the timing counters in the PCI Express IP core operate
faster than specified in the PCI Express specification.This
parameter should usually be set to 1, but can be set to 0 if there
is a need to simulate the true time-out values.
Figure 15–2
presents a high level view of the
(altpcietb_bfm_ep_example_chaining_pipen1b)
15–22.
Description
Chapter 15: Testbench and Design Example
EP Model
December 2010 Altera Corporation
Table
Root Port Testbench
15–1.