IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 122

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

5–38
Table 5–16. Configuration Space Register Descriptions (Part 2 of 3)
PCI Express Compiler User Guide
Register
cfg_rootcsr
cfg_seccsr
cfg_secbus
cfg_subbus
cfg_io_bas
cfg_io_lim
cfg_np_bas
cfg_np_lim
cfg_pr_bas
cfg_pr_lim
cfg_pmcsr
cfg_msixcsr
Width
8
16
8
8
20
20
12
12
44
12
32
16
Dir
O
O
O
O
O
O
O
O
O
O
O
O
Description
Root control and status register of the PCI-Express capability. This
register is only available in root port mode.
Secondary bus control and status register of the PCI-Express
capability. This register is only available in root port mode.
Secondary bus number. Available in root port mode.
Subordinate bus number. Available in root port mode.
IO base windows of the Type1 configuration space. This register is
only available in root port mode.
IO limit windows of the Type1 configuration space. This register is
only available in root port mode.
Non-prefetchable base windows of the Type1 configuration space.
This register is only available in root port mode.
Non-prefetchable limit windows of the Type1 configuration space.
This register is only available in root port mode.
Prefetchable base windows of the Type1 configuration space. This
register is only available in root port mode.
Prefetchable limit windows of the Type1 configuration space.
Available in root port mode.
cfg_pmcsr[31:16] is power management control and
cfg_pmcsr[15:0]the power management status register. This
register is only available in root port mode.
MSI-X message control. Duplicated for each function
implementing MSI-X.
December 2010 Altera Corporation
Chapter 5: IP Core Interfaces
Register
Reference
Table 6–7 on
page 6–4
0x0A0 (Gen1)
Table 6–8 on
page 6–5
0x0A0 (Gen2)
Table 6–3 on
page 6–3
0x01C
Table 6–3 on
page 6–3
0x018
Table 6–3 on
page 6–3
0x018
Table 6–3 on
page 6–3
0x01C
Table 6–8 on
page 6–5
0x01C
Table 3–2 on
page 3–5
EXP ROM
Table 3–2 on
page 3–5
EXP ROM
Table 6–3 on
page 6–3
0x024 and
Table 3–2
Prefetchable
memory
Table 6–3 on
page 6–3
0x024
Table 3–2
Prefetchable
memory
Table 6–6 on
page 6–4
0x07C
Table 6–5 on
page 6–4
0x068
Avalon-ST Interface