IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 275
IP-PCIE/1
Manufacturer Part Number
IP-PCIE/1
Description
IP CORE - PCI Express X1 Lane
Manufacturer
Altera
Type
MegaCorer
Specifications of IP-PCIE/1
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Express Compiler, x1 Link Width
License
Initial License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
- Current page: 275 of 362
- Download datasheet (7Mb)
Chapter 15: Testbench and Design Example
BFM Procedures and Functions
Table 15–46. himage (std_logic_vector) Function
Table 15–47. himage (integer) Function
Table 15–48. himage1
December 2010 Altera Corporation
Location
Syntax
Argument
Return
Location
Syntax
Arguments num
Return
Location
syntax
Argument
Return range
Verilog HDL Formatting Functions
string:= himage(vec)
vec
string
string:= himage(num, hlen)
hlen
string
altpcietb_bfm_log.vhd
altpcietb_bfm_log.vhd
string:= himage(vec)
vec
string
altpcietb_bfm_log.v
himage (std_logic_vector) Function
The himage function is a utility routine that returns a hexadecimal string
representation of the std_logic_vector argument. The string is the length of the
std_logic_vector divided by four (rounded up). You can control the length of the
string by padding or truncating the argument as needed.
himage (integer) Function
The himage function is a utility routine that returns a hexadecimal string
representation of the integer argument. The string is the length specified by the hlen
argument.
The following procedures and functions are available in the Verilog HDL include file
altpcietb_bfm_log.v that uses the altpcietb_bfm_log_common.v module,
instantiated at the top level of the testbench. This section outlines formatting
functions that are only used by Verilog HDL. All these functions take one argument of
a specified length and return a vector of a specified length.
himage1
This function creates a one-digit hexadecimal string representation of the input
argument that can be concatenated into a larger message string and passed to
ebfm_display.
This argument is a std_logic_vector that is converted to a hexadecimal string.
Hexadecimal formatted string representation of the argument
Argument of type integer that is converted to a hexadecimal string.
Length of the returned string. The string is truncated or padded with 0s on the right as
needed.
Hexadecimal formatted string representation of the argument.
Input data type reg with a range of 3:0.
Returns a 1-digit hexadecimal representation of the input argument. Return data is type
reg with a range of 8:1
PCI Express Compiler User Guide
15–47
Related parts for IP-PCIE/1
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
IP CORE - 32-bit 66MHz PCI Master/Target
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE - 64-bit 66MHz PCI Master/Target
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE - 32-bit 66MHz PCI Target
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE - 64-bit 66MHz PCI Target
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCI/MT32
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCI/MT64
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCI/T32
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE Renewal Of IP-PCI/T64
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE - PCI Express X1 And X4 Lanes
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP CORE - PCI Express X1 X4 And X8 Lanes
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
IP NIOS II MEGACORE
Manufacturer:
Altera
Datasheet: