IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 153

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 6: Register Descriptions
PCI Express Avalon-MM Bridge Control Register Content
Table 6–15. PCI Express-to-Avalon-MM Mailbox Registers, Read/Write
Table 6–16. Avalon-MM-to-PCI Express Mailbox Registers, read-only
December 2010 Altera Corporation
0x0800
0x0804
0x0808
0x080C
0x0810
0x0814
0x0818
0x081C
0x0900
0x0904
0x0908
0x090C
0x0910
0x0914
0x0918
0x091C
Address
Address
Avalon-MM-to-PCI Express Address Translation Table
A2P_MAILBOX0
A2P_MAILBOX1
A2P_MAILBOX2
A2P_MAILBOX3
A2P_MAILBOX4
A2P_MAILBOX5
P2A_MAILBOX0
P2A_MAILBOX1
P2A_MAILBOX2
P2A_MAILBOX3
P2A_MAILBOX4
P2A_MAILBOX5
P2A_MAILBOX6
P2A_MAILBOX7
A2P_MAILBOX6
A2P_MAILBOX7
The PCI Express-to-Avalon-MM mailbox registers are writable at the addresses shown
in
Avalon-MM interrupt status register to be set to a one.
The Avalon-MM-to-PCI Express mailbox registers are read at the addresses shown in
Table
mailbox information after being signaled by the corresponding bits in the PCI Express
interrupt enable register.
The Avalon-MM-to-PCI Express address translation table is writable using the CRA
slave port if dynamic translation is enabled.
Table
Name
Name
6–16. The PCI Express root complex should use these addresses to read the
6–15. Writing to one of these registers causes the corresponding bit in the
Access
Access
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
PCI Express-to-Avalon-MM Mailbox 0
PCI Express-to-Avalon-MM Mailbox 1
PCI Express-to-Avalon-MM Mailbox 2
PCI Express-to-Avalon-MM Mailbox 3
PCI Express-to-Avalon-MM Mailbox 4
PCI Express-to-Avalon-MM Mailbox 5
PCI Express-to-Avalon-MM Mailbox 6
PCI Express-to-Avalon-MM Mailbox 7
Avalon-MM-to-PCI Express Mailbox 0
Avalon-MM-to-PCI Express Mailbox 1
Avalon-MM-to-PCI Express Mailbox 2
Avalon-MM-to-PCI Express Mailbox 3
Avalon-MM-to-PCI Express Mailbox 4
Avalon-MM-to-PCI Express Mailbox 5
Avalon-MM-to-PCI Express Mailbox 6
Avalon-MM-to-PCI Express Mailbox 7
Description
Description
Address Range: 0x0900-0x091F
Address Range: 0x800-0x0815
PCI Express Compiler User Guide
6–9