IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 224

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

14–8
Table 14–2. 16-bit PHY Interface Signals (Part 2 of 3)
PCI Express Compiler User Guide
pipe_txclk
rxdata0_ext[15:0]
rxdatak0_ext[1:0]
rxelecidle0_ext
rxpolarity0_ext
rxstatus0_ext[1:0]
rxvalid0_ext
txcompl0_ext
txdata0_ext[15:0]
txdatak0_ext[1:0]
txelecidle0_ext
rxdata1_ext[15:0]
rxdatak1_ext[1:0]
rxelecidle1_ext
rxpolarity1_ext
rxstatus1_ext[1:0]
rxvalid1_ext
txcompl1_ext
txdata1_ext[15:0]
txdatak1_ext[1:0]
txelecidle1_ext
rxdata2_ext[15:0]
rxdatak2_ext[1:0]
rxelecidle2_ext
rxpolarity2_ext
rxstatus2_ext[1:0]
rxvalid2_ext
txcompl2_ext
txdata2_ext[15:0]
txdatak2_ext[1:0]
txelecidle2_ext
rxdata3_ext[15:0]
rxdatak3_ext[1:0]
Signal Name
Direction
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Source synchronous transmit clock signal for clocking
TX Data and Control signals going to the PHY.
Pipe interface lane 0 RX data signals, carries the
parallel received data.
Pipe interface lane 0 RX data K-character flags.
Pipe interface lane 0 RX electrical idle indication.
Pipe interface lane 0 RX polarity inversion control.
Pipe interface lane 0 RX status flags.
Pipe interface lane 0 RX valid indication.
Pipe interface lane 0 TX compliance control.
Pipe interface lane 0 TX data signals, carries the
parallel transmit data.
Pipe interface lane 0 TX data K-character flags.
Pipe interface lane 0 TX electrical Idle Control.
Pipe interface lane 1 RX data signals, carries the
parallel received data.
Pipe interface lane 1 RX data K-character flags.
Pipe interface lane 1 RX electrical idle indication.
Pipe interface lane 1 RX polarity inversion control.
Pipe interface lane 1 RX status flags.
Pipe interface lane 1 RX valid indication.
Pipe interface lane 1 TX compliance control.
Pipe interface lane 1 TX data signals, carries the
parallel transmit data.
Pipe interface lane 1 TX data K-character flags.
Pipe interface lane 1 TX electrical idle control.
Pipe interface lane 2 RX data signals, carries the
parallel received data.
Pipe interface lane 2 RX data K-character flags.
Pipe interface lane 2 RX electrical idle indication.
Pipe interface lane 2 RX polarity inversion control.
Pipe interface lane 2 RX status flags.
Pipe interface lane 2 RX valid indication.
Pipe interface lane 2 TX compliance control.
Pipe interface lane 2 TX data signals, carries the
parallel transmit data.
Pipe interface lane 2 TX data K-character flags.
Pipe interface lane 2 TX electrical idle control.
Pipe interface lane 3 RX data signals, carries the
parallel received data.
Pipe interface lane 3 RX data K-character flags.
Description
December 2010 Altera Corporation
Only in modes that
have the TXClk
Always
Always
Always
Always
Always
Always
Always
Always
Always
Always
Only in ×4
Only in ×4
Only in ×4
Only in ×4
Only in ×4
Only in ×4
Only in ×4
Only in ×4
Only in ×4
Only in ×4
Only in ×4
Only in ×4
Only in ×4
Only in ×4
Only in ×4
Only in ×4
Only in ×4
Only in ×4
Only in ×4
Only in ×4
Only in ×4
Only in ×4
Chapter 14: External PHYs
External PHY Support
Availability