IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 12

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

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PCI Express Compiler User Guide
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Feature rich:
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Easy to use:
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New features in the 10.1 release:
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Support for ×1, ×2, ×4, and ×8 configurations. You can select the ×2 lane
configuration for the Cyclone IV GX without down configuring a ×4
configuration.
Optional end-to-end cyclic redundancy code (ECRC) generation and checking
and advanced error reporting (AER) for high reliability applications.
Extensive maximum payload size support:
Easy parameterization.
Substantial on-chip resource savings and guaranteed timing closing using the
PCI Express hard IP implementation.
Easy adoption with no license requirement for the hard IP implementation.
Example designs to get started.
SOPC Builder support.
Support for Stratix V devices has the following new features:
Support for the Gen1 ×1 soft IP implementation in Cyclone IV GX device with
the Avalon-ST interface.
Support for the hard IP implementation in the Arria II GZ device with the
Avalon-ST interface and the following capabilities:
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Stratix IV GX and Stratix V GX hard IP—Up to 2 KBytes (128, 256, 512, 1,024,
or 2,048 bytes).
Arria II GX and Cyclone IV GX hard IP—Up to 256 bytes (128 or 256).
Soft IP Implementations—Up to 2 KBytes (128, 256, 512, 1,024, or 2,048 bytes).
256-bit interface for the Stratix V hard IP implementation.
Target design example demonstrating the 256-bit interface that connects the
PCI Express IP core to a root complex and a downstream application with
the 256-bit interface.
Verilog HDL and VHDL simulation support.
Gen1 ×1, ×4 64-bit interface, Gen1 ×8 128-bit interface.
Gen2 ×1, 64-bit interface, Gen2 ×4, 128-bit interface.
Single virtual channel.
December 2010 Altera Corporation
Chapter 1: Datasheet
Features