IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 303

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter :
TLP Packet Format with Data Payload
Table A–8. Message without Data
Table A–9. Completion without Data
Table A–10. Completion Locked without Data
TLP Packet Format with Data Payload
Table A–11. Memory Write Request, 32-Bit Addressing
Table A–12. Memory Write Request, 64-Bit Addressing
December 2010 Altera Corporation
Byte 0
Byte 4
Byte 8
Byte 12
Notes to
(1) Not supported in Avalon-MM.
Byte 0
Byte 4
Byte 8
Byte 12
Byte 0
Byte 4
Byte 8
Byte 12
Byte 0
Byte 4
Byte 8
Byte 12
Table
0 0 1 1 0
+0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
0 0 0 0 1 0 1 1 0
+0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
0 1 0 0 0 0 0 0 0 TC
+0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
0 0 0 0 1 0 1 0 0 TC
+0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
A–8:
Table A–11
payload.
r
2
Completer ID
Requester ID
Completer ID
Requester ID
Requester ID
Requester ID
r
1
r
0
+1
through
+1
+1
+1
0 TC
TC
A–5
0 0 0 0 TD
0 0 0 0 TD
0 0 0 0 TD
0 0 0 0 TD
show the content for transaction layer packets with a data
Vendor defined or all zeros
Vendor defined or all zeros
Address[31:2]
Reserved
Reserved
Reserved
+2
+2
+2
+2
Status
Status
6
EP
6
6
EP
6
EP
EP
5 4 3 2 1 0 7 6 5 4 3 2 1 0
Att
r
5 4 3 2 1 0 7 6 5 4 3 2 1 0
5 4 3 2 1 0 7 6 5 4 3 2 1 0
Att
5 4 3 2 1 0 7 6 5 4 3 2 1 0
Att
r
0 0 0 0 0 0 0 0 0 0 0 0 0 0
Tag
r
Tag
Tag
B
B
Tag
0 0
0 0
0 0
+3
0
Byte Count
Byte Count
+3
0
PCI Express Compiler User Guide
+3
+3
Last BE
Length
Length
Length
Message Code
Lower Address
Lower Address
First BE
0 0
A–3