IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 16

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

1–6
Figure 1–1. PCI Express Hard IP High-Level Block Diagram
Note to
(1) Stratix IV GX devices have two virtual channels.
(2) LMI stands for Local Management Interface.
(3) Stratix V GX devices does not require the adapter.
(4) Configuration via PCI Express (CvPCIe) is only available in Stratix V devices.
PCI Express Compiler User Guide
Transceivers
Figure
PCS
1–1:
f
PMA
The hard IP implementation includes all of the required and most of the optional
features of the specification for the transaction, data link, and physical layers.
Depending upon the device you choose, one to four instances of the hard PCI Express
IP core are available. These instances can be configured to include any combination of
root port and endpoint designs to meet your system requirements. A single device can
also use instances of both the soft and hard IP PCI Express IP core.
provides a high-level block diagram of the hard IP implementation.
This user guide includes a design example and testbench that you can configure as a
root port (RP) or endpoint (EP). You can use these design examples as a starting point
to create and test your own root port and endpoint designs.
The purpose of the PCI Express Compiler User Guide is to explain how to use the PCI
Express IP core and not to explain the PCI Express protocol. Although there is
inevitable overlap between the two documents, this document should be used in
conjunction with an understanding of the following PCI Express specifications:
PHY Interface for the PCI Express Architecture PCI Express 3.0
Specification 1.0a, 1.1, or
PCI Express Hard IP
Buffer
Retry
Protocol Stack
2.0.
PCI Express
PCI Express Reconfiguration
Channel
Virtual
Buffer
RX
(Note 1) (2) (3) (4)
Configuration Block
CvPCIe (4)
Interface
TL
Clock & Reset
Selection
Reconfig
Adapter
Note (3)
PCIe
LMI
and
December 2010 Altera Corporation
PCI Express Base
Figure 1–1
Chapter 1: Datasheet
FPGA Fabric
Test, Debug &
General Description
Configuration
Application
Logic
Layer