IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 126

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

5–42
Table 5–19. Reconfiguration Block Signals (Hard IP Implementation)
Table 5–20. Power Management Signals
PCI Express Compiler User Guide
avs_pcie_reconfig_address[7:0]
avs_pcie_reconfig_byteeenable[1:0]
avs_pcie_reconfig_chipselect
avs_pcie_reconfig_write
avs_pcie_reconfig_writedata[15:0]
avs_pcie_reconfig_waitrequest
avs_pcie_reconfig_read
avs_pcie_reconfig_readdata[15:0]
avs_pcie_reconfig_readdatavalid
avs_pcie_reconfig_clk
avs_pcie_reconfig_rstn
pme_to_cr
pme_to_sr
cfg_pmcsr[31:0]
Signal
Power Management Signals
f
Signal
For a detailed description of the Avalon-MM protocol, refer to the Avalon Memory-
Mapped Interfaces chapter in the
Table 5–20
in configurations using the Avalon-ST interface or Descriptor/Data interface.
I/O
O
O
I
Power management turn off control register.
Root port—When this signal is asserted, the root port sends the PME_turn_off message.
Endpoint—This signal is asserted to acknowledge the PME_turn_off message by sending
pme_to_ack to the root port.
Power management turn off status register.
Root port—This signal is asserted for 1 clock cycle when the root port receives the
pme_turn_off acknowledge message.
Endpoint—This signal is asserted when the endpoint receives the PME_turn_off message
from the root port. For the soft IP implementation, it is asserted until pme_to_cr is
asserted. For the hard IP implementation, it is asserted for one cycle.
Power management capabilities register. This register is read-only and provides information
related to power management for a specific function. Refer to
additional information. This signal only exists in soft IP implementation. In the hard IP
implementation, this information is accessed through the configuration interface. Refer to
“Configuration Space Signals—Hard IP Implementation” on page
shows the IP core’s power management signals. These signals are available
I/O
O
O
O
I
I
I
I
I
I
I
I
A 8-bit address.
Byte enables, currently unused.
Chipselect.
Write signal.
16-bit write data bus.
Asserted when unable to respond to a read or write request.
When asserted, the control signals to the slave remain constant.
waitrequest can be asserted during idle cycles. An
Avalon-MM master may initiate a transaction when
waitrequest is asserted.
Read signal.
16-bit read data bus.
Read data valid signal.
Reconfiguration clock for the hard IP implementation. This
clock should not exceed 50MHz.
Active-low Avalon-MM reset. Resets all of the dynamic
reconfiguration registers to their default values as described in
Table 13–1 on page
Avalon Interface
Description
Specifications.
13–2.
Description
Table 5–21
December 2010 Altera Corporation
5–31.
Chapter 5: IP Core Interfaces
and
Avalon-ST Interface
Table 5–22
for