IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 336

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

B–30
PCI Express Compiler User Guide
RX Datapath
The RX datapath contains the RX boundary registers (for incremental compile) and a
bridge to transport data from the PCI Express IP core interface to the Avalon-ST
interface. The bridge autonomously acks all packets received from the PCI Express IP
core. For simplicity, the rx_abort and rx_retry features of the IP core are not used,
and RX_mask is loosely supported. (Refer to
details.) The RX datapath also provides an optional message-dropping feature that is
enabled by default. The feature acknowledges PCI Express message packets from the
PCI Express IP core, but does not pass them to the user application. The user can
optionally allow messages to pass to the application by setting the DROP_MESSAGE
parameter in altpcierd_icm_rxbridge.v to 1’b0. The latency through the ICM RX
datapath is approximately four clock cycles.
TX Datapath
The TX datapath contains the TX boundary registers (for incremental compile) and a
bridge to transport data from the Avalon-ST interface to the PCI Express IP core
interface. A data FIFO buffers the Avalon-ST data from the user application until the
PCI Express IP core accepts it. The TX datapath also implements an NPBypass
function for deadlock prevention. When the PCI Express IP core runs out of
non-posted (NP) credits, the ICM allows completions and posted requests to bypass
NP requests until credits become available. The ICM handles any NP requests
pending in the ICM when credits run out and asserts the tx_mask signal to the user
application to indicate that it should stop sending NP requests. The latency through
the ICM TX datapath is approximately five clock cycles.
MSI Datapath
The MSI datapath contains the MSI boundary registers (for incremental compile) and
a bridge to transport data from the Avalon-ST interface to the PCI Express IP core
interface. The ICM maintains packet ordering between the TX and MSI datapaths. In
this design example, the MSI interface supports low-bandwidth MSI requests. For
example, not more than one MSI request can coincide with a single TX packet. The
MSI interface assumes that the MSI function in the PCI Express IP core is enabled. For
other applications, you may need to modify this module to include internal buffering,
MSI-throttling at the application, and so on.
Sideband Datapath
The sideband interface contains boundary registers for non-timing critical signals
such as configuration signals. (Refer to
ICM Files
This section lists and briefly describes the ICM files. The PCI Express MegaWizard
generates all these ICM files placing them in the
<variation name>_examples\common\incremental_compile_module folder.
Table B–17 on page B–36
Table B–14 on page B–32
Incremental Compile Module for Descriptor/Data Examples
December 2010 Altera Corporation
for details.)
for further
Chapter :