IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 70

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

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Data Link Layer
Figure 4–8. Data Link Layer
PCI Express Compiler User Guide
Tx Transaction Layer
Packet Description & Data
To Transaction Layer
Packet Description & Data
Tx Flow Control Credits
Configuration Space
Rx Transation Layer
Rx Flow Control Credits
The data link layer is located between the transaction layer and the physical layer. It is
responsible for maintaining packet integrity and for communication (by data link
layer packet transmission) at the PCI Express link level (as opposed to component
communication by transaction layer packet transmission in the interconnect fabric).
The data link layer is responsible for the following functions:
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■
■
■
■
Figure 4–8
The data link layer has the following subblocks:
Link management through the reception and transmission of data link layer
packets, which are used for the following functions:
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■
■
Data integrity through generation and checking of CRCs for transaction layer
packets and data link layer packets
Transaction layer packet retransmission in case of NAK data link layer packet
reception using the retry buffer
Management of the retry buffer
Link retraining requests in case of error through the LTSSM of the physical layer
To initialize and update flow control credits for each virtual channel
For power management of data link layer packet reception and transmission
To transmit and receive ACK/NACK packets
Transaction Layer
Packet Checker
Transaction Layer
Packet Generator
illustrates the architecture of the data link layer.
Retry Buffer
Ack/Nack
Packets
Generator
DLLP
Management
Checker
Function
Power
DLLP
Tx Arbitration
Data Link Control
& Management
State Machine
To Physical Layer
Rx Packets
Tx Packets
December 2010 Altera Corporation
Chapter 4: IP Core Architecture
& Status
Control
Data Path
Data Path
Transmit
Receive
Data Link Layer