IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 194

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

10–4
PCI Express Interrupts for Root Ports
PCI Express Compiler User Guide
Figure 10–6
app_int_ack indicates that the Deassert_INTA message TLP has been sent.
Figure 10–6. Legacy Interrupt Deassertion
Table 10–1
allocated and 2 in which only 4 are allocated.
Table 10–1. MSI Messages Requested, Allocated, and Mapped
MSI interrupts generated for hot plug, power management events, and system errors
always use TC0. MSI interrupts generated by the application layer can use any traffic
class. For example, a DMA that generates an MSI at the end of a transmission can use
the same traffic control as was used to transfer data.
In root port mode, the PCI Express IP core receives interrupts through two different
mechanisms:
■
■
Normally, the root port services rather than sends interrupts; however, in two
circumstances the root port can send an interrupt to itself to record error conditions:
■
■
The Root Error Status register reports the status of error messages. The root error
status register is part of the PCI Express AER extended capability structure. It is
located at offset 0x830 of the configuration space registers.
System error
Hot plug and power management event
Application
MSI—Root ports receive MSI interrupts through the Avalon-ST RX TLP of type
MWr. This is a memory mapped mechanism.
Legacy—Legacy interrupts are translated into TLPs of type Message Interrupt
which is sent to the application layer using the int_status[3:0] pins.
When the AER option is enabled, the aer_msi_num[4:0] signal indicates which
MSI is being sent to the root complex when an error is logged in the AER
capability structure. This mechanism is an alternative to using the serr_out signal.
The aer_msi_num[4:0] is only used for root ports and you must set it to a constant
value. It cannot toggle during operation.
If the root port detects a power management event. The pex_msi_num[4:0] signal
is used by power management or hot plug to determine the offset between the
base message interrupt number and the message interrupt number to send
through MSI. The user must set pex_msi_num[4:0]to a fixed value.
app_int_ack
app_int_sts
describes 3 example implementations; 1 in which all 32 MSI messages are
illustrates the timing for deassertion of legacy interrupts. The assertion of
clk
MSI
29:0
32
31
30
PCI Express Interrupts for Root Ports
Allocated
December 2010 Altera Corporation
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Chapter 10: Interrupts
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