IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 226

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

14–10
Table 14–3. 8-bit PHY Interface Signals (Part 2 of 2)
Selecting an External PHY
PCI Express Compiler User Guide
rxdatak1_ext
rxelecidle1_ext
rxpolarity1_ext
rxstatus1_ext[1:0]
rxvalid1_ext
txcompl1_ext
txdata1_ext[7:0]
txdatak1_ext
txelecidle1_ext
rxdata2_ext[7:0]
rxdatak2_ext
rxelecidle2_ext
rxpolarity2_ext
rxstatus2_ext[1:0]
rxvalid2_ext
txcompl2_ext
txdata2_ext[7:0]
txdatak2_ext
txelecidle2_ext
rxdata3_ext[7:0]
rxdatak3_ext
rxelecidle3_ext
rxpolarity3_ext
rxstatus3_ext[1:0]
rxvalid3_ext
txcompl3_ext
txdata3_ext[7:0]
txdatak3_ext
txelecidle3_ext
Signal Name
You can select an external PHY and set the appropriate options in the MegaWizard
Plug-In Manager flow or in the SOPC Builder flow, but the available options may
differ. The following description uses the MegaWizard Plug-In Manager flow.
You can select one of the following PHY options on the MegaWizard interface System
Settings page:
Direction
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Pipe interface lane 1 RX data K-character flag.
Pipe interface lane 1 RX electrical idle indication.
Pipe interface lane 1 RX polarity inversion control.
Pipe interface lane 1 RX status flags.
Pipe interface lane 1 RX valid indication.
Pipe interface lane 1 TX compliance control.
Pipe interface lane 1 TX data signals, carries the parallel
transmit data.
Pipe interface lane 1 TX data K-character flag.
Pipe interface lane 1 TX electrical idle control.
Pipe interface lane 2 RX data signals, carries the parallel
received data.
Pipe interface lane 2 RX data K-character flag.
Pipe interface lane 2 RX electrical idle indication.
Pipe interface lane 2 RX polarity inversion control.
Pipe interface lane 2 RX status flags.
Pipe interface lane 2 RX valid indication.
Pipe interface lane 2 TX compliance control.
Pipe interface lane 2 TX data signals, carries the parallel
transmit data.
Pipe interface lane 2 TX data K-character flag.
Pipe interface lane 2 TX electrical idle control.
Pipe interface lane 3 RX data signals, carries the parallel
received data.
Pipe interface lane 3 RX data K-character flag.
Pipe interface lane 3 RX electrical idle indication.
Pipe interface lane 3 RX polarity inversion control.
Pipe interface lane 3 RX status flags.
Pipe interface lane 3 RX valid indication.
Pipe interface lane 3 TX compliance control.
Pipe interface lane 3 TX data signals, carries the parallel
transmit data.
Pipe interface lane 3 TX data K-character flag.
Pipe interface lane 3 TX electrical idle control.
Description
December 2010 Altera Corporation
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Chapter 14: External PHYs
Selecting an External PHY
Availability