IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 296

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

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Compile the Design
Program a Device
PCI Express Compiler User Guide
f
1
You can use the same testbench to simulate the Completer-Only single dword IP core
by changing the settings in the driver file. For the Verilog HDL design example, edit
the altpcietb_bfm_driver.v file in the
c:\sopc_pci\pci_express_compiler_examples\sopc\testbench directory to enable
target memory tests and specify the completer-only single dword variant. Set the
following parameters in the file to one:
You can use the Quartus II software to compile the system generated by SOPC
Builder.
To compile your design, follow these steps:
1. In the Quartus II software, open the pcie_top.qpf project.
2. On the View menu, point to Utility Windows, and then click Tcl Console.
3. To source the script that sets the required constraints, type the following command
4. On the Processing menu, click Start Compilation.
5. After compilation, expand the TimeQuest Timing Analyzer folder in the
After you compile your design, you can program your targeted Altera device and
verify your design in hardware.
For more information about IP functional simulation models, see the
Designs
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If you are running the VHDL design example, edit the altpcietb_bfm_driver.vhd
in the c:\sopc_pci\pci_express_compiler_examples\sopc\testbench directory to
set the following parameters to one.
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in the Tcl Console window:
Compilation Report. Note whether the timing constraints are achieved in the
Compilation Report.
If your design does not initially meet the timing constraints, you can find the
optimal Fitter settings for your design by using the Design Space Explorer. To use
the Design Space Explorer, click Launch Design Space Explorer on the tools
menu.
source pci_compiler_0.tcl r
parameter RUN_TGT_MEM_TST = 1;
parameter RUN_DMA_MEM_TST = 0;
parameter AVALON_MM_LITE = 1;
RUN_TGT_MEM_TST : std_logic := '1';
RUN_DMA_MEM_TST : std_logic := '0';
AVALON_MM_LITE : std_logic := '1';
chapter in volume 3 of the Quartus II Handbook.
Chapter 16: SOPC Builder Design Example
December 2010 Altera Corporation
Simulating Altera
Compile the Design