IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 313

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter :
Descriptor/Data Interface
Figure B–5. RX Three Transactions without Data Payloads Waveform
December 2010 Altera Corporation
Descriptor
Signals
Data
Signals
rx_desc[135:128]
rx_desc[127:64]
rx_data[63:32]
rx_desc[63:0]
rx_data[31:0]
Transaction without Data Payload
In
data payloads:
In clock cycles 4, 7, and 12, the IP core updates flow control credits after each
transaction layer packet has either been acknowledged or aborted. When necessary,
the IP core generates flow control DLLPs to advertise flow control credit levels.
The I/O read request initiated at clock cycle 8 is not acknowledged until clock cycle 11
with assertion of rx_ack. The relatively late acknowledgment could be due to possible
congestion.
Retried Transaction and Masked Non-Posted Transactions
When the application layer can no longer accept non-posted requests, one of two
things happen: either the application layer requests the packet be resent or it asserts
rx_mask. For the duration of rx_mask, the IP core masks all non-posted transactions
and reprioritizes waiting transactions in favor of posted and completion transactions.
When the application layer can once again accept non-posted transactions, rx_mask is
deasserted and priority is given to all non-posted transactions that have accumulated
in the receive buffer.
rx_be[7:0]
rx_mask
rx_abort
Figure
rx_retry
■
■
■
rx_ack
rx_req
rx_ws
rx_dfr
rx_dv
Memory read request (64-bit addressing mode)
Memory read request (32-bit addressing mode)
I/O read request
clk
B–5, the IP core receives three consecutive transactions, none of which have
1
2
MEMRD64
3
valid
valid
4
5
MEMRD32
6
valid
valid
7
8
9
PCI Express Compiler User Guide
I/O RD
valid
valid
11
B–7