IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 74

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

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PCI Express Avalon-MM Bridge
PCI Express Compiler User Guide
The PCI Express Compiler configured using the SOPC Builder design flow uses the
PCI Express Compiler’s Avalon-MM bridge module to connect the PCI Express link to
the system interconnect fabric. The bridge facilitates the design of PCI Express
endpoints that include SOPC Builder components.
The full-featured PCI Express Avalon-MM bridge, shown in
three possible Avalon-MM ports: a bursting master, an optional bursting slave, and an
optional non-bursting slave. The PCI Express Avalon-MM bridge comprises the
following three modules:
■
■
TX Slave Module—This optional 64-bit bursting, Avalon-MM dynamic addressing
slave port propagates read and write requests of up to 4 KBytes in size from the
system interconnect fabric to the PCI Express link. The bridge translates requests
from the interconnect fabric to PCI Express request packets.
RX Master Module—This 64-bit bursting Avalon-MM master port propagates PCI
Express requests, converting them to bursting read or write requests to the system
interconnect fabric.
When the multilane lane deskew block is first enabled, each FIFO begins writing
after the first COM is detected. If all lanes have not detected a COM symbol after 7
clock cycles, they are reset and the resynchronization process restarts, or else the
RX alignment function recreates a 64-bit data word which is sent to the data link
layer.
December 2010 Altera Corporation
Figure
Chapter 4: IP Core Architecture
PCI Express Avalon-MM Bridge
4–10, provides