IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 151

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 6: Register Descriptions
PCI Express Avalon-MM Bridge Control Register Content
Table 6–11. Avalon-MM Control and Status Register Address Spaces
Table 6–12. PCI Express Avalon-MM Bridge Register Map
Table 6–13. Avalon-MM to PCI Express Interrupt Status Register (Part 1 of 2)
December 2010 Altera Corporation
0x0000-0x0FFF
0x1000-0x1FFF
0x2000-0x2FFF
0x3000-0x3FFF
0x0040
0x0050
0x0800-0x081F
0x0900-0x091F
0x1000-0x1FFF
0x3060
0x3070
0x3A00-0x3A1F
0x3B00-0x3B1F
31:24
23
22
Address Range
Address
Bit
Range
Avalon-MM to PCI Express Interrupt Registers
1
Reserved
A2P_MAILBOX_INT7
A2P_MAILBOX_INT6
Registers typically intended for access by PCI Express processors only. This includes PCI Express
interrupt enable controls, Write access to the PCI Express Avalon-MM bridge mailbox registers, and
read access to Avalon-MM-to-PCI Express mailbox registers.
Avalon-MM-to-PCI Express address translation tables. Depending on the system design these may be
accessed by PCI Express processors, Avalon-MM processors, or both.
Reserved.
Registers typically intended for access by Avalon-MM processors only. These include Avalon-MM
Interrupt enable controls, write access to the Avalon-MM-to-PCI Express mailbox registers, and read
access to PCI Express Avalon-MM bridge mailbox registers.
PCI Express Interrupt Status Register
PCI Express Interrupt Enable Register
PCI Express Avalon-MM Bridge Mailbox Registers, read/write
Avalon-MM-to-PCI Express Mailbox Registers, read-only
Avalon-MM-to PCI Express Address Translation Table
Avalon-MM Interrupt Status Register
Avalon-MM Interrupt Enable Register
Avalon-MM-to-PCI Express Mailbox Registers, read/write
PCI Express Avalon-MM Bridge Mailbox Registers, read-only
The four subregions are described
The data returned for a read issued to any undefined address in this range is
unpredictable.
The complete map of PCI Express Avalon-MM bridge registers is shown in
The registers in this section contain status of various signals in the PCI Express
Avalon-MM bridge logic and allow PCI Express interrupts to be asserted when
enabled. These registers can be accessed by other PCI Express root complexes only;
however, hardware does not prevent other Avalon-MM masters from accessing them.
Table 6–13
be asserted.
Name
shows the status of all conditions that can cause a PCI Express interrupt to
Access
RW1C
RW1C
—
Address Space Usage
Table
1 when the A2P_MAILBOX7 is written to
1 when the A2P_MAILBOX6 is written to
Register
6–11:
Description
—
PCI Express Compiler User Guide
Address: 0x0040
Table
6–12:
6–7