IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 188

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

9–6
Figure 9–1. Using Lane Reversal to Solve PCB Routing Problems
Instantiating Multiple PCI Express IP Cores
PCI Express Compiler User Guide
Clock and Signal Requirements for Devices with Transceivers
No Lane Reversal
Results in PCB Routing Challenge
Figure 9–1
endpoint on the top side of the PCB. Connecting the lanes without lane reversal
creates routing problems. Using lane reversal, solves the problem.
PCI Express
If you want to instantiate multiple PCI Express IP cores, a few additional steps are
required. The following sections outline these steps.
When your design contains multiple IP cores that use the Arria GX or Stratix II GX
transceiver (ALTGX or ALT2GXB) megafunction or the Arria II GX, Cyclone IV GX, or
Stratix IV GX transceiver (ALTGX) megafunction, you must ensure that the
cal_blk_clk input and gxb_powerdown signals are connected properly.
Whether you use the MegaWizard Plug-In Manager or the SOPC Builder design flow,
you must ensure that the cal_blk_clk input to each PCI Express IP core (or any other
megafunction or user logic that uses the ALTGX or ALT2GXB megafunction) is driven
by the same calibration clock source.
When you use SOPC Builder to create a system with multiple PCI Express IP core
variations, you must filter the signals in the System Contents tab to display the clock
connections, as described in steps
connections, ensure that cal_blk_clk and any other IP core variations in the system
that use transceivers are connected to the cal_blk_clk port on the PCI Express IP core
variation.
In either the MegaWizard Plug-In Manager or SOPC Builder flow, when you merge
multiple PCI Express IP cores in a single transceiver block, the same signal must drive
gxb_powerdown to each of the PCI Express IP core variations and other IP cores, and
user logic that use the ALTGX or ALT2GXB IP cores.
Root Port
0
1
2
3
illustrates a PCI Express card with two, ×4 IP cores, a root port and an
3
2
1
0
PCI Express
Endpoint
no lane
reversal
2
With Lane Reversal
Signals Route Easily
and
PCI Express
Root Port
3
on
page
0
1
2
3
16–7. After you display the clock
Instantiating Multiple PCI Express IP Cores
0
1
2
3
PCI Express
Endpoint
reversal
lane
December 2010 Altera Corporation
Chapter 9: Optional Features