IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 134

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

5–50
Table 5–26. Avalon-MM RX Master Interface Signals
PCI Express Compiler User Guide
RXmRead_o
RXmWrite_o
RXmAddress_o[31:0]
RXmWriteData_o[<n>:0]
RXmByteEnable_o[<n>:0]
RXmBurstCount_o[9:0]
RXmWaitRequest_i
RXmReadData_i[<n>:0]
RXmReadDataValid_i
RXmIrq_i
RXmIrqNum_i[5:0]
RXmResetRequest_o
RX Avalon-MM Master Signals
64-Bit Bursting TX Avalon-MM Slave Signals
Signal SOPC Builder
This Avalon-MM master port propagates PCI Express requests to the SOPC Builder
system. For the full-feature IP core it propagates requests as bursting reads or writes.
For the completer-only IP core, requests are a single dword.
Master interface ports.
This optional Avalon-MM bursting slave port propagates requests from the system
interconnect fabric to the full-featured PCI Express IP core. Requests from the system
interconnect fabric are translated into PCI Express request packets. Incoming requests
can be up to 4 KByte s in size. For better performance, Altera recommends using smaller
read request size (a maximum 512 bytes).
I/O
O
O
O
O
O
O
O
I
I
I
I
I
Asserted by the core to request a read.
Asserted by the core to request a write to an Avalon-MM slave.
The address of the Avalon-MM slave being accessed.
RX data being written to slave. <n> = 63 for the full-featured IP core. <n>
= 31 for the completer-only, single dword IP core.
Byte enable for write data. <n> = 63 for the full-featured IP core. <n> = 31
for the completer-only, single dword IP core.
The burst count, measured in qwords, of the RX write or read request. The
width indicates the maximum data, up to 4 KBytes, that can be requested.
Asserted by the external Avalon-MM slave to hold data transfer.
Read data returned from Avalon-MM slave in response to a read request.
This data is sent to the IP core through the TX interface. <n> = 7 for the
full-featured IP core. <n> = 3 for the completer-only, single dword IP core.
Asserted by the system interconnect fabric to indicate that the read data on
is valid.
Indicates an interrupt request asserted from the system interconnect fabric.
This signal is only available when the control register access port is
enabled.
Indicates the ID of the interrupt request being asserted. This signal is only
available when the control register access port is enabled.
This reset signal is asserted if any of the following conditions are true:
npor, l2_exit, hotrst_exist, dlup_exit, or reset_n are asserted, or
ltssm == 5’h10. Refer to
reset logic when using the PCI Express IP core in SOPC Builder.
Figure 5–42 on page 5–52
Description
December 2010 Altera Corporation
Table 5–26
Avalon-MM Application Interface
Chapter 5: IP Core Interfaces
for schematic of the
lists the RX