IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 123

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: IP Core Interfaces
Avalon-ST Interface
Table 5–16. Configuration Space Register Descriptions (Part 3 of 3)
Table 5–17. Configuration Space Signals (Part 1 of 2)(Soft IP Implementation)
December 2010 Altera Corporation
Register
cfg_msicsr
cfg_tcvcmap
cfg_busdev
cfg_tcvcmap[23:0]
cfg_busdev[12:0]
cfg_prmcsr[31:0]
Configuration Space Signals—Soft IP Implementation
Signal
Width
16
24
13
The signals in
registers that the application layer may need to access. These signals are available in
configurations using the Avalon-ST interface (soft IP implementation) or the
descriptor/data Interface.
I/O
O
O
O
Dir
O
O
O
Configuration traffic class/virtual channel mapping: The application layer uses this signal
to generate a transaction layer packet mapped to the appropriate virtual channel based on
the traffic class of the packet.
Configuration bus device: This signal generates a transaction ID for each transaction layer
packet, and indicates the bus and device number of the IP core. Because the IP core only
implements one function, the function number of the transaction ID must be set to 000b.
Configuration primary control status register. The content of this register controls the PCI
status.
cfg_tcvcmap[2:0]: Mapping for TC0 (always 0).
cfg_tcvcmap[5:3]: Mapping for TC1.
cfg_tcvcmap[8:6]: Mapping for TC2.
cfg_tcvcmap[11:9]: Mapping for TC3.
cfg_tcvcmap[14:12]: Mapping for TC4.
cfg_tcvcmap[17:15]: Mapping for TC5.
cfg_tcvcmap[20:18]: Mapping for TC6.
cfg_tcvcmap[23:21]: Mapping for TC7.
cfg_busdev[12:5]: Bus number.
cfg_busdev[4:0]: Device number.
Description
MSI message control. Duplicated for each function implementing
MSI.
Configuration traffic class (TC)/virtual channel (VC) mapping. The
application layer uses this signal to generate a transaction layer
packet mapped to the appropriate virtual channel based on the
traffic class of the packet.
Bus/device number captured by or programmed in the core.
Table 5–17
cfg_tcvcmap[2:0]: Mapping for TC0 (always 0).
cfg_tcvcmap[5:3]: Mapping for TC1.
cfg_tcvcmap[8:6]: Mapping for TC2.
cfg_tcvcmap[11:9]: Mapping for TC3.
cfg_tcvcmap[14:12]: Mapping for TC4.
cfg_tcvcmap[17:15]: Mapping for TC5.
cfg_tcvcmap[20:18]: Mapping for TC6.
cfg_tcvcmap[23:21]: Mapping for TC7.
reflect the current values of several configuration space
Description
PCI Express Compiler User Guide
Register
Reference
Table 6–4 on
page 6–3
0x050
Table 6–9 on
page 6–5
Table A–6
0x08
5–39