IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 298

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

17–2
PCI Express Compiler User Guide
f
f
Check Link Training and Status State Machine (dl_ltssm[4:0])
The PCI Express IP core dl_ltssm[4:0] bus encodes the status of LTSSM. The LTSSM
state machine reflects the physical layer’s progress through the link training process.
For a complete description of the states these signals encode, refer to
Training Signals” on page
link is up, the LTSSM should remain stable in the L0 state.
When link issues occur, you can monitor dl_ltssm[4:0] to determine whether link
training fails before reaching the L0 state or the link was initially established (L0), but
then lost due to an additional link training issue. If you have link training issues, you
can check the actual link status in hardware using the SignalTap II logic analyzer. The
LTSSM encodings indicate the LTSSM state of the physical layer as it proceeds
through the link training process.
For more information about link training, refer to the “Link Training and Status State
Machine (LTSSM) Descriptions” section of
For more information about SignalTap, refer to the
SignalTap II Embedded Logic Analyzer
Check PIPE Interface
Because the LTSSM signals reflect the behavior of one side of the PCI Express link,
you may find it difficult to determine the root cause of the link issue solely by
monitoring these signals. Monitoring the PIPE interface signals in addition to the
dl_ltssm bus provides greater visibility.
The PIPE interface is specified by Intel. This interface defines the MAC/PCS
functional partitioning and defines the interface signals for these two sublayers. Using
the SignalTap logic analyzer to monitor the PIPE interface signals provides more
information about the devices that form the link.
During link training and initialization, different pre-defined physical layer packets
(PLPs), known as ordered sets are exchanged between the two devices on all lanes. All
of these ordered sets have special symbols (K codes) that carry important information
to allow two connected devices to exchange capabilities, such as link width, link data
rate, lane reversal, lane-to-lane de-skew, and so on. You can track the ordered sets in
the link initialization and training on both sides of the link to help you diagnose link
issues. You can use SignalTap logic analyzer to determine the behavior. The following
signals are some of the most important for diagnosing bring-up issues:
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■
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If you are using the soft IP implementation of the PCI Express IP core, you can see the
PIPE interface at the pins of your device. If you are using the hard IP implementation,
you can monitor the PIPE signals through the test_out bus.
txdata<n>_ext[15:0]
control being transmitted from Altera PCIe IP core to the other device.
rxdata<n>_ext[15:0]
control received by Altera PCIe IP core from the other device.
phystatus<n>_ext—this signal communicates completion of several PHY
requests.
rxstatus<n>_ext[2:0]—this signal encodes receive status and error codes for the
receive data stream and receiver detection.
/ txdatak<n>_ext[1:0] —these signals show the data and
/ rxdatak<n>_ext[1:0] —these signals show the data and
5–24. When link training completes successfully and the
chapter in volume 3 of the Quartus II Handbook.
PCI Express Base Specification
Design Debugging Using the
December 2010 Altera Corporation
Hardware Bring-Up Issues
Chapter 17: Debugging
“Reset and Link
2.0.