IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 210

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

13–4
Table 13–1. Dynamically Reconfigurable Registers in the Hard IP Implementation (Part 3 of 7)
PCI Express Compiler User Guide
0x91
0x92
0x93
0x94
0x95
Address
Bits
15:10
15:10 Slot Power Limit Value.
15:3
15:8
1:0
7:2 Max Link width.
9:8
6:0 [6]: Hot-plug capable.
9:7 Reserved.
1:0 Reserved.
7:0
15
2
Role-Based error reporting. (Available in PCI Express Base
Specification Revision 1.1 compliant Cores only.)In 1.1
compliant cores, this bit should be set to 1.
L0s Active State power management support.
L1 Active State power management support.
L1 exit latency common clock.
L1 exit latency separated clock. The following encodings
are defined:
[0]: Attention button implemented on the chassis.
[1]: Power controller present.
[2]: Manually Operated Retention Latch (MRL) sensor
present.
[3]: Attention indicator present for a root port, switch, or
bridge.
[4]: Power indicator present for a root port, switch, or
bridge.
[5]: Hot-plug surprise: When this bit set to1, a device can
be removed from this slot without prior notification.
Electromechanical Interlock present (Available in PCI
Express Base Specification Revision 1.1 compliant IP
cores only.)
Physical Slot Number (if slot implemented). This signal
indicates the physical slot number associated with this
port. It must be unique within the fabric.
NFTS_SEPCLK. The number of fast training sequences for
the separate clock.
NFTS_COMCLK. The number of fast training sequences
for the common clock.
Slot Power Limit Scale.
b’000 – Less than 1 µs.
b’001 – 1 µs to less than 2 µs.
b’010 – 2 µs to less than 4 µs.
b’011 – 4 µs to less than 8 µs.
b’100 – 8 µs to less than 16 µs.
b’101 – 16 µs to less than 32 µs.
b’110 – 32 µs to 64 µs.
b’111 – More than 64 µs.
Description
Chapter 13: Reconfiguration and Offset Cancellation
b’00000000
b’10000000
b’10000000
b’0000000
b’000100
b’000000
Default
Value
b’000
b’00
b’01
b’1
b’0
b’0
—
December 2010 Altera Corporation
Table 6–10 on page
Correctable Error Mask
register
Table 6–8 on page
Slot Capability register
Table 6–8 on page
Link Capability register
Table 6–8 on page
Link Capability register
Table 6–8 on page
Link Capability register
Table 6–8 on page
Slot Capability register
Table 6–8 on page
Slot Capability register
Additional Information
Dynamic Reconfiguration
—
6–5,
6–5,
6–5,
6–5,
6–5,
6–5,
6–6,