IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 294

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

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PCI Express Compiler User Guide
1
5. To generate waveform output for the simulation, type the following command at
Some versions of ModelSim SE turn on design optimization by default. Optimization
may eliminate design nodes which are referenced in your wave_presets.do file. In this
case, the w alias fails. You can ignore this failure if you want to run an optimized
simulation. However, if you want to see the simulation signals, you can disable the
optimized compilation by setting VoptFlow = 0 in your modelsim.ini file.
6. To simulate the design, type the following command at the simulator prompt:
7. Exit the ModelSim tool after it reports successful completion.
the simulator command prompt:
The PCI Express Compiler test driver performs the following transactions with
display status of the transactions displayed in the ModelSim simulation message
window:
■
■
■
■
■
do wave_presets.do r
run -all r
Various configuration accesses to the PCI Express IP core in your system after
the link is initialized
Setup of the Address Translation Table for requests that are coming from the
DMA component
Setup of the DMA controller to read 4 KBytes of data from the Root Port BFM’s
shared memory
Setup of the DMA controller to write the same 4 KBytes of data back to the
Root Port BFM’s shared memory
Data comparison and report of any mismatch
Chapter 16: SOPC Builder Design Example
December 2010 Altera Corporation
Simulate the SOPC Builder System