IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 257

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 15: Testbench and Design Example
Root Port BFM
December 2010 Altera Corporation
3. Assigns values to all the endpoint BAR registers. The BAR addresses are assigned
4. Based on the above BAR assignments, the root port configuration space address
5. The endpoint PCI control register is set to enable master transactions, memory
by the algorithm outlined below.
a. I/O BARs are assigned smallest to largest starting just above the ending
b. The 32-bit non-prefetchable memory BARs are assigned smallest to largest,
c. Assignment of the 32-bit prefetchable and 64-bit prefetchable memory BARS
d. If the addr_map_4GB_limit input to the ebfm_cfg_rp_ep is set to 0, then the 64-
The above algorithm cannot always assign values to all BARs when there are a few
very large (1 GByte or greater) 32-bit BARs. Although assigning addresses to all
BARs may be possible, a more complex algorithm would be required to effectively
assign these addresses. However, such a configuration is unlikely to be useful in
real systems. If the procedure is unable to assign the BARs, it displays an error
message and stops the simulation.
windows are assigned to encompass the valid BAR address ranges.
address decoding, and I/O address decoding.
address of BFM shared memory in I/O space and continuing as needed
throughout a full 32-bit I/O space. Refer to
information.
starting just above the ending address of BFM shared memory in memory
space and continuing as needed throughout a full 32-bit memory space.
are based on the value of the addr_map_4GB_limit input to the
ebfm_cfg_rp_ep. The default value of the addr_map_4GB_limit is 0.
If the addr_map_4GB_limit input to the ebfm_cfg_rp_ep is set to 0, then the 32-
bit prefetchable memory BARs are assigned largest to smallest, starting at the
top of 32-bit memory space and continuing as needed down to the ending
address of the last 32-bit non-prefetchable BAR.
However, if the addr_map_4GB_limit input is set to 1, the address map is
limited to 4 GByte, the 32-bit and 64-bit prefetchable memory BARs are
assigned largest to smallest, starting at the top of the 32-bit memory space and
continuing as needed down to the ending address of the last 32-bit non-
prefetchable BAR.
bit prefetchable memory BARs are assigned smallest to largest starting at the 4
GByte address assigning memory ascending above the 4 GByte limit
throughout the full 64-bit memory space. Refer to
If the addr_map_4GB_limit input to the ebfm_cfg_rp_ep is set to 1, then the 32-
bit and the 64-bit prefetchable memory BARs are assigned largest to smallest
starting at the 4 GByte address and assigning memory by descending below
the 4 GByte address to addresses memory as needed down to the ending
address of the last 32-bit non-prefetchable BAR. Refer to
page
15–31.
Figure 15–9 on page 15–33
Figure 15–8 on page
PCI Express Compiler User Guide
Figure 15–7 on
for more
15–32.
15–29