IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 72

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–14
Figure 4–9. Physical Layer
PCI Express Compiler User Guide
Rx Packets
Tx Packets
To Data Link Layer
■
■
■
The hard IP implementation includes the following additional functionality:
■
■
■
■
■
Figure 4–9
The physical layer is subdivided by the PIPE Interface Specification into two layers
(bracketed horizontally in
■
■
Generation
SKIP
Control & Status
Initializing the link
Scrambling/descrambling and 8B10B encoding/decoding of 2.5 Gbps (Gen1) or
5.0 Gbps (Gen2) per lane 8B10B
Serializing and deserializing data
PIPE 2.0 Interface Gen1/Gen2: 8-bit@250/500 MHz (fixed width, variable clock)
Auto speed negotiation (Gen2)
Training sequence transmission and decode
Hardware autonomous speed control
Auto lane reversal
Media Access Controller (MAC) Layer—The MAC layer includes the Link
Training and Status state machine (LTSSM) and the scrambling/descrambling and
multilane deskew functions.
PHY Layer—The PHY layer includes the 8B10B encode/decode functions, elastic
buffering, and serialization/deserialization functions.
Lane n
Lane 0
Lane n
Lane 0
Descrambler
Descrambler
Scrambler
Scrambler
illustrates the physical layer architecture.
MAC Layer
State Machine
LTSSM
Rx MAC
Rx MAC
Figure
Lane
Lane
Interface
PIPE
4–9):
Emulation Logic
Decoder
Decoder
Encoder
Encoder
8B10B
8B10B
8B10B
8B10B
PIPE
PHY layer
Elastic
Elastic
Buffer
Buffer
December 2010 Altera Corporation
Chapter 4: IP Core Architecture
Rx+ / Rx-
Rx+ / Rx-
Tx+ / Tx-
Tx+ / Tx-
To Link
Transmit
Data Path
Receive
Data Path
Physical Layer