IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 334

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

B–28
Table B–12. <variation_name>_icm Interface Descriptions
PCI Express Compiler User Guide
Transmit Datapath
Receive Datapath
Configuration
Completion interfaces
Interrupt
Test Interface
Global Interface
PIPE Interface
Maximum Completion
Space Signals
Note to
(1) Cfg_tcvcmap is available from the ICM module, but not wired to the <variation_name>_icm ports. Refer to
details.
Signal Group
Table
B–12:
()
1
<variation_name>_icm Partition
When you generate a PCI Express IP core, the MegaWizard produces module,
<variation_name>_icm in the subdirectory
<variation_name>_examples\common\incremental_compile_module, as a
wrapper file that contains the IP core and the ICM module. (Refer to
Your application connects to this wrapper file. The wrapper interface resembles the
PCI Express IP core interface, but replaces it with an Avalon-ST interface. (Refer to
Table
The wrapper interface omits some signals from the IP core to maximize circuit
optimization across the partition boundary. However, all of the IP core signals are still
available on the IP core instance and can be wired to the wrapper interface by editing
the <variation_name>_icm file as required.
By setting this wrapper module as a design partition, you can preserve timing of the
IP core using the incremental synthesis flow.
Table B–12
ICM Avalon-ST TX interface. These signals include tx_stream_valid0, tx_stream_data0,
tx_stream_ready0, tx_stream_cred0, and tx_stream_mask0. Refer to
page B–33
ICM interface. These signals include rx_stream_valid0, rx_stream_data0,
rx_stream_ready0, and rx_stream_mask0. Refer to
Part of ICM sideband interface. These signals include cfg_busdev_icm, cfg_devcsr_icm, and
cfg_linkcsr_icm.
Part of ICM sideband interface. These signals include cpl_pending_icm, cpl_err_icm,
pex_msi_num_icm, and app_int_sts_icm. Refer to
ICM Avalon-ST MSI interface. These signals include msi_stream_valid0, msi_stream_data0,
and msi_stream_ready0. Refer to
Part of ICM sideband signals; includes test_out_icm. Refer to
details.
IP core signals; includes refclk, clk125_in, clk125_out, npor, srst, crst, ls_exit,
hotrst_exit, and dlup_exit. Refer to
IP core signals; includes tx, rx, pipe_mode, txdata0_ext, txdatak0_ext,
txdetectrx0_ext, txelecidle0_ext, txcompliance0_ext, rxpolarity0_ext,
powerdown0_ext, rxdata0_ext, rxdatak0_ext, rxvalid0_ext, phystatus0_ext,
rxelecidle0_ext, rxstatus0_ext, txdata0_ext, txdatak0_ext, txdetectrx0_ext,
txelecidle0_ext, txcompliance0_ext, rxpolarity0_ext, powerdown0_ext,
rxdata0_ext, rxdatak0_ext, rxvalid0_ext, phystatus0_ext, rxelecidle0_ext, and
rxstatus0_ext. Refer
This signal is ko_cpl_spc_vc<n>, and is not available at the <variation_name>_icm ports ().
Instead, this static signal is regenerated for the user in the <variation_name>_example_pipen1b
module.
B–12.)
describes the <variation_name>_icm interfaces.
for details.
Chapter 5, IP Core Interfaces
Table B–16 on page B–35
Chapter 5, IP Core Interfaces
Description
Incremental Compile Module for Descriptor/Data Examples
for details.
Table B–17 on page B–36
Table B–14 on page B–32
for details.
Table B–17 on page B–36
December 2010 Altera Corporation
Table B–17 on page B–36
for details.
Table B–15 on
Figure
for details.
for details.
B–23.)
Chapter :
for
for