IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 290

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

16–6
Complete the Connections in SOPC Builder
Table 16–6. SOPC Builder Connections
PCI Express Compiler User Guide
pci_express_compiler bar2_Non_Prefetchable Avalon
master port
pci_express_compiler bar2_Non_Prefetchable Avalon
master port
dma irq Interrupt sender
dma read_master Avalon master port
dma read_master Avalon master port
dma write_master Avalon master port
dma write_master Avalon master port
Specify Clock and Address Assignments
Make Connection From:
In SOPC Builder, hovering the mouse over the Connections column displays the
potential connection points between components, represented as dots on connecting
wires. A filled dot shows that a connection is made; an open dot shows a potential
connection point. Clicking a dot toggles the connection status. To complete this
design, create the following connections:
1. Connect the pci_express_compiler bar1_0_Prefetchable Avalon master port to
2. Repeat step 1 to make the connections listed in
To complete the system, follow these instructions to specify clock and address
assignments:
1. Under Clock Settings, double-click in the MHz box, type 125, and press Enter.
2. To add a second external clock, cal_clk, for calibration, follow these steps:
the onchip_mem s1 Avalon slave port using the following procedure:
a. Click the bar1_0_Prefetchable port then hover in the Connections column to
b. Click the open dot at the intersection of the onchip_mem s1 port and the
a. Under Clock Settings, click Add. A new clock, clk_1, appears in the Name
b. Double-click clk_1 and type cal_clk, then press Enter.
c. To specify the frequency, double-click the MHz box and type the desired
By default, clock names are not displayed. To display clock names in the Module
Name column and the clocks in the Clock column in the System Contents tab,
click Filters to display the Filters dialog box. In the Filter list, select All. Then close
the Filters dialog box.
display possible connections.
pci_express_compiler bar1_0_Prefetchable to create a connection.
box.
frequency. cal_clk can have a frequency range of 10-125 MHz.
dma control_port_slave Avalon slave port
pci_express_compiler Control_Register_access Avalon
slave port
pci_express_compiler RxmIrq Interrupt Receiver
onchip_mem s1 Avalon slave port
pci_express_compiler TX_Interface Avalon slave port
onchip_mem s1 Avalon slave port
pci_express_compiler TX_Interface Avalon slave port
Table
Chapter 16: SOPC Builder Design Example
Complete the Connections in SOPC Builder
16–6.
To:
December 2010 Altera Corporation