IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 254

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

15–26
Root Port BFM
PCI Express Compiler User Guide
The basic root port BFM provides a VHDL procedure-based or Verilog HDL
task-based interface for requesting transactions that are issued to the PCI Express link.
The root port BFM also handles requests received from the PCI Express link.
Figure 15–6
Figure 15–6. Root Port BFM
The functionality of each of the modules included in
■
A set of procedures is provided to read, write, fill, and check the shared memory from
the BFM driver. For details on these procedures, see
Procedures” on page
■
BFM shared memory (altpcietb_bfm_shmem VHDL package or Verilog HDL
include file)—The root port BFM is based on the BFM memory that is used for the
following purposes:
■
■
■
■
■
BFM Read/Write Request Procedures/Functions (altpcietb_bfm_rdwr VHDL
package or Verilog HDL include file)— This package provides the basic BFM
procedure calls for PCI Express read and write requests. For details on these
procedures, see
Storing data received with all completions from the PCI Express link.
Storing data received with all write transactions received from the PCI Express
link.
Sourcing data for all completions in response to read transactions received
from the PCI Express link.
Sourcing data for most write transactions issued to the PCI Express link. The
only exception is certain BFM write procedures that have a four-byte field of
write data passed in the call.
Storing a data structure that contains the sizes of and the values programmed
in the BARs of the endpoint.
provides an overview of the root port BFM.
Root Port BFM
(altpcietb_bfm_shmem)
BFM Shared Memory
Root Port RTL Model (altpcietb_bfm_rp_top_x8_pipen1b)
BFM Log Interface
(altpcietb_bfm_log)
“BFM Read and Write Procedures” on page
(altpcietb_bfm_rpvar_64b_x8_pipen1b)
15–40.
IP Functional Simulation
Model of the Root
Port Interface
BFM Read/Write Shared
Request Procedures
(altpcietb_bfm_rdwr)
(altpcietb_bfm_vcintf)
(altpcietb_bfm_vcintf)
“BFM Shared Memory Access
Figure 15–6
Chapter 15: Testbench and Design Example
(altpcietb_bfm_configure)
VC0 Interface
VC1 Interface
BFM Request Interface
(altpcietb_bfm_req_intf)
BFM Configuration
Procedures
December 2010 Altera Corporation
15–34.
is explained below.
Root Port BFM