IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 131

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 5: IP Core Interfaces
Avalon-MM Application Interface
Figure 5–40. Signals in the SOPC Builder Soft or Hard Full-Featured IP Core with Avalon-MM Interface
Notes to
(1) Available in Stratix II GX, Stratix IV GX, Arria GX, and HardCopy IV GX devices. The reconfig_fromgxb is a single wire for Stratix II GX and
(2) Available in Stratix II GX, Stratix IV GX, Arria GX, and HardCopy IV GX devices. For Stratix II GX and Arria GX reconfig_togxb, <n> = 2. For
(3) Signals in blue are for simulation only.
December 2010 Altera Corporation
Arria GX. For Stratix IV GX, <n> = 16 for ×1 and ×4 IP cores and <n> = 33 the ×8 IP core.
Stratix IV GX, <n> = 3.
Figure
Avalon-MM Rx
Master Port
Avalon-MM Tx
Avalon-MM
Slave Port
Slave Port
64-Bit
32-Bit
CRA
64-Bit
Reset &
5–40:
Clock
Status
Figure 5–40
SOPC Builder design flow. Your parameterization may not include some of the ports.
The Avalon-MM signals are shown on the left side of this figure.
CraIrq_o
CraReadData_o[31:0]
CraWaitRequest_o
CraAddress_i[11:0]
CraByteEnable_i[3:0]
CraChipSelect_i
CraRead_i
CraWrite_i
CraWriteData_i[31:0]
RxmWrite_o
RxmRead_o
RxmAddress_o[31:0]
RxmWriteData_o[63:0]
RxmByteEnable_o[7:0]
RxmBurstCount_o[9:0]
RxmWaitRequest_i
RxmReadDataValid_i
RxmReadData_i[63:0]
RxmIrq_i
RxmIrqNum_i[5:0]
RxmResetRequest_o
TxsChipSelect_i
TxsRead_i
TxsWrite_i
TxsAddress_i[WIDTH-1:0]
TxsBurstCount_i[9:0]
TxsWriteData_i[63:0]
TxsByteEnable_i[7:0]
TxsReadDataValid_o
TxsReadData_o[63:0]
TxsWaitRequest_o
refclk
clk125_out
AvlClk_i
reset_n
pcie_rstn
suc_spd_neg
shows all the signals of a full-featured PCI Express IP core available in the
Signals in the PCI Express MegaCore Function
with Avalon-MM Interface
(1)
(2)
reconfig_fromgxb[ <n> :0]
test_out[511:0] or [9:0]
powerdown <n> _ext[1:0]
reconfig_togxb[ <n> :0]
(test_out is optional)
rxdata <n> _ext[15:0]
txdata <n> _ext[15:0]
txdatak <n> _ext[1:0]
rxdatak <n> _ext[1:0]
powerdown0_ext[1:0]
txelectidle <n> _ext
rxelectidle <n> _ext
gxb_powerdown
rxstatus0_ext[2:0]
rxpolarity <n> _ext
rxstatus0_ext[2:0]
xphy_pll_areset
xphy_pll_locked
txcompl <n> _ext
rxvalid <n> _ext
rxdata0_ext[7:0]
txdata0_ext[7:0]
rxelectidle0_ext
txdetectrx_ext
txelectidle0_ext
phystatus_ext
reconfig_clk
test_in[31:0]
rxpolarity0_ext
txdetectrx_ext
phystatus_ext
cal_blk_clk
txcompl0_ext
txdatak0_ext
rxdatak0_ext
pipe_mode
rxvalid0_ext
rate_ext
rx[3:0]
tx[3:0]
PCI Express Compiler User Guide
Test
Interface
Implementation
Transceiver
(Repeat for lanes
Implementation
8-Bit PIPE
Simulation
16-Bit PIPE
for x1 and x4
1-3 in x4)
1-Bit Serial
Control
Soft IP
Only
(3)
Hard IP
5–47