IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 82

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

4–24
Figure 4–13. PCI Express Avalon-MM Interrupts
PCI Express Compiler User Guide
Avalon-MM-to-PCI-Express
Interrupt Status and Interrupt
Enable Register Bits
A2P_MAILBOX_INT7
A2P_MAILBOX_INT6
A2P_MAILBOX_INT5
A2P_MAILBOX_INT4
A2P_MAILBOX_INT3
A2P_MAILBOX_INT2
A2P_MAILBOX_INT1
A2P_MAILBOX_INT0
AV_IRQ_ASSERTED
A2P_MB_IRQ7
A2P_MB_IRQ6
A2P_MB_IRQ5
A2P_MB_IRQ4
A2P_MB_IRQ3
A2P_MB_IRQ2
A2P_MB_IRQ1
A2P_MB_IRQ0
(Configuration Space Message Control Register[0])
(Configuration Space Command Register [10])
AVL_IRQ
Figure 4–13
The PCI Express Avalon-MM bridge selects either MSI or legacy interrupts
automatically based on the standard interrupt controls in the PCI Express
configuration space registers. The Interrupt Disable bit, which is bit 10 of the
Command register
bit, which is bit 0 of the MSI Control Status register in the MSI capability shown in
Table 11–3 on page
interrupt can be enabled at a time.
Generation of Avalon-MM Interrupts
Generation of Avalon-MM interrupts requires the instantiation of the CRA slave
module where the interrupt registers and control logic are implemented. The CRA
slave port has an Avalon-MM Interrupt (CraIrq_o) output. A write access to an
Avalon-MM mailbox register sets one of the P2A_MAILBOX_INT<n> bits in the
Express to Avalon-MM Interrupt Status Register Address: 0x3060” on page 6–11
asserts the CraIrq_o output, if enabled. Software can enable the interrupt by writing
to the
page 6–11
the appropriate serviced interrupt status bit in the PCI-Express-to-Avalon-MM
interrupt status register and ensure that there is no other interrupt status pending.
“PCI Express to Avalon-MM Interrupt Enable Register Address: 0x3070” on
through the CRA slave. After servicing the interrupt, software must clear
shows the logic for the entire PCI Express interrupt generation process.
(Table
11–5, can be used to enable MSI interrupts. Only one type of
Interrupt Disable
MSI Enable
11–1) can be used to disable legacy interrupts. The MSI enable
D
SET
CLR
Q
Q
PCI Express Virtual INTA signalling
(When signal rises ASSERT_INTA Message Sent)
(When signal falls DEASSERT_INTA Message Sent)
December 2010 Altera Corporation
Chapter 4: IP Core Architecture
PCI Express Avalon-MM Bridge
MSI Request
“PCI
and