IP-PCIE/1 Altera, IP-PCIE/1 Datasheet - Page 325

• Manufacturer Part Number: IP-PCIE/1
• Description: IP CORE - PCI Express X1 Lane
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCIE/1

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x1 Link Width
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter :
Descriptor/Data Interface
Figure B–15. TX Transaction Layer Not Ready to Accept Packet
December 2010 Altera Corporation
Descriptor
Signals
Data
Signals
tx_desc[127:0]
tx_data[63:32]
tx_data[31:0]
Figure B–15
before write data can be transferred. Prior to the start of a transaction (for example,
tx_req being asserted), note that the tx_ws signal is set low for the ×1 and ×4
configurations and is set high for the ×8 configuration.
Possible Wait State Insertion
If the IP core is not initialized with the maximum potential lanes, data transfer is
necessarily hindered. Refer to
write transaction of 8 dwords. Address bit 2 is set to 0.
In clock cycle three, data transfer can begin immediately as long as the transfer buffer
is not full.
In clock cycle five, once the buffer is full and the IP core implements wait states to
throttle transmission; four clock cycles are required per transfer instead of one
because the IP core is not configured with the maximum possible number of lanes
implemented.
tx_ack
tx_req
tx_ws
tx_err
tx_dfr
tx_dv
clk
1
shows that the application layer must wait to receive an acknowledge
2
3
Figure
4
B–17. The application transmits a 32-bit memory
MEMWR32
5
DW0
6
PCI Express Compiler User Guide
7
8
9
B–19