IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet
IP-PCI/MT32
Specifications of IP-PCI/MT32
Related parts for IP-PCI/MT32
IP-PCI/MT32 Summary of contents
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... Innovation Drive San Jose, CA 95134 www.altera.com PCI Compiler User Guide Compiler Version: Document Date: January 2011 10.1 ...
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... PCI Compiler User Guide Version 10.1 Altera Corporation ...
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... Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al- tera products are protected under numerous U ...
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... PCI Compiler User Guide Version 10.1 Altera Corporation ...
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... Section I. PCI Compiler With MegaWizard Plug-In Manager Flow Chapter 1. Getting Started Design Flow ............................................................................................................................................ 1–1 PCI MegaCore Function Design Walkthrough ................................................................................. 1–2 Create a New Quartus II Project .................................................................................................... 1–2 Launch IP Toolbench ....................................................................................................................... 1–4 Step 1: Parameterize ......................................................................................................................... 1–5 Step 2: Set Up Simulation ................................................................................................................ 1–7 Step 3: Generate ................................................................................................................................ 1–7 Simulate the Design ............................................................................................................................... 1–9 Simulation in the Quartus II Software ........................................................................................ 1– ...
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... Advanced PCI MegaCore Function Features .................................................................................... 2–3 Optional Registers ....................................................................................................................... 2–3 Optional Interrupt Capabilities ................................................................................................. 2–4 Master Features ........................................................................................................................... 2–4 Variation File Parameters ..................................................................................................................... 2–7 Chapter 3. Functional Description Functional Overview ............................................................................................................................. 3–1 Target Device Signals & Signal Assertion .................................................................................... 3–6 Master Device Signals & Signal Assertion .................................................................................... 3–9 PCI Bus Signals .................................................................................................................................... 3–11 Parameterized Configuration Register Signals .......................................................................... 3– ...
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... Target Mode Operation ............................................................................................................... 3–131 64-Bit Address, 64-Bit Data Single-Cycle Target Read Transaction ................................ 3–132 Master Mode Operation .............................................................................................................. 3–134 64-Bit Address, 64-Bit Data Master Burst Memory Read Transaction ............................ 3–134 Chapter 4. Testbench General Description ............................................................................................................................... 4–1 Altera Corporation PCI Compiler Version 10.1 vii PCI Compiler User Guide ...
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... Program a Device ................................................................................................................................ 5–14 Upgrading Systems from a Previous Version ................................................................................. 5–15 Chapter 6. Parameter Settings System Options-1 ................................................................................................................................... 6–1 PCI Device Mode ........................................................................................................................ 6–1 PCI Target Performance ............................................................................................................. 6–3 PCI Master Performance ............................................................................................................ 6–5 Value of Multiple Pending Reads ....................................................................................................... 6–6 viii PCI Compiler User Guide PCI Compiler Version 10.1 Altera Corporation ...
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... PCI MegaCore Function ............................................................................................................. 7–5 PCI Bus Arbiter ........................................................................................................................... 7–6 Other PCI-Avalon Bridge Modules .......................................................................................... 7–6 PCI Operational Modes ................................................................................................................... 7–6 PCI Target-Only Peripheral Mode Operation ........................................................................ 7–6 PCI Master/Target Peripheral Mode Operation .................................................................... 7–8 PCI Host-Bridge Device Mode Operation ............................................................................. 7–10 Performance Profiles ...................................................................................................................... 7–11 Target Performance .................................................................................................................. 7–12 Master Performance .................................................................................................................. 7–12 Interface Signals ................................................................................................................................... 7– ...
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... FILE IO section .......................................................................................................................... 8–13 PROCEDURES and TASKS sections ...................................................................................... 8–13 Bus Monitor (monitor) ................................................................................................................... 8–13 Arbiter (arbiter) .............................................................................................................................. 8–14 Pull Up (pull_up) ........................................................................................................................... 8–14 Simulation Flow ................................................................................................................................... 8–15 Appendix A. Using PCI Constraint File Tcl Scripts Introduction ........................................................................................................................................... A–1 PCI Constraint Files .............................................................................................................................. A–1 Simultaneous Switching Noise (SSN) Considerations .................................................................... A–2 Additional Options ............................................................................................................................... A–3 x PCI Compiler User Guide PCI Compiler Version 10 ...
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... A–6 Upgrading Assignments from a Previous Version of PCI Compiler ............................................ A–6 Upgrading PCI Assignments Containing Nondefault PCI Pin Names .................................. A–7 Additional Information Revision History ............................................................................................................................... Info–i How to Contact Altera .................................................................................................................... Info–ii Typographic Conventions ............................................................................................................. Info–iii Altera Corporation PCI Compiler Version 10.1 xi PCI Compiler User Guide ...
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... Contents xii PCI Compiler User Guide PCI Compiler Version 10.1 Altera Corporation ...
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... This option allows you to build a complete PCI system—component- by-component—using an automatically-generated sytem interconnect fabric. The SOPC Builder uses the PCI-Avalon®- Memory-Mapped (Avalon-MM) bridge to connect the PCI bus to the interconnect, allowing you to easily create any system that includes one or more of the Avalon-MM peripherals. PCI Compiler Version 10.1 1 ...
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... HardCopy device family. It can be used in production designs with caution. PCI Compiler Version 10.1 Description 10.1 January 2011 IP-PCI/MT64, IP-PCI/T64, IP-PCI/MT32, IP-PCI/T32 MegaCore function: 0011, pci_mt64 MegaCore function: 0025, pci_t64 MegaCore function: 0022, pci_mt32 MegaCore function: 0024 ...
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... Table 2 functions for each Altera device family. Table 2. Device Family Support Arria Arria II GX Cyclone Cyclone II Cyclone III Cyclone III LS Cyclone IV GX HardCopy II HardCopy III HardCopy IV (E, GX) MAX Stratix Stratix GX Stratix II Stratix II GX Stratix III Stratix IV (E, GX) Other device families Note to ...
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... BARs) and expansion ROM base address Non-parameterized registers: command, status, header type 0, ● latency timer, cache line size, interrupt pin, interrupt line Host bridge application support IP Toolbench wizard-driven interface makes it easy to generate a custom variation of a PCI MegaCore function PCI target features: Capabilities list pointer support ● ...
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... General This section provides a general description of the following: Description ■ ■ ■ ■ PCI MegaCore Functions The PCI MegaCore functions are hardware-tested, high-performance, flexible implementations of PCI interfaces. These functions handle the PCI protocol and timing requirements internally. The back-end interface ...
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... The PCI testbench, provided in Verilog HDL and VHDL, facilitates the design and verification of systems that implement any of the PCI MegaCore functions. You can build a PCI behavioral simulation environment by using components of the PCI testbench, the IP functional simulation model of your PCI MegaCore function variation, and the rest of your Verilog HDL or VHDL design. ...
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... With this flow, you specify system components and choose system options from a rich set of features, and the SOPC Builder then automatically generates the interconnect logic and simulation environment. Thus, you define and generate a complete system in dramatically less time than manually integrating separate IP blocks. 1 Altera Corporation January 2011 ...
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... General Description For example, PCI Compiler with SOPC Builder flow; the dashed-lines indicate pre-existing components that are added to the design via the SOPC Builder graphical user interface (GUI). When comparing Figure option requires far less user customization. Figure 2. PCI-to-DDR2 SDRAM Design Using the PCI Compiler With SOPC Builder Flow ...
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... Altera Corporation January 2011 summarizes the guidelines for selecting a particular flow over SOPC Builder Flow You would like to quickly integrate multiple system blocks. You are creating a new PCI design. You have limited PCI bus protocol experience. Dramatically faster time-to-market Requires minimal PCI bus protocol design expertise ...
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... MegaCore function and a reference design, and PCI bus agents such PCI Compiler User Guide More control of the system feature set Can design directly from the PCI interface to peripheral devices Can access local-side interface to reduce clock cycles and achieve higher bandwidth Requires manual integration of system modules ...
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... Ethernet network adapter, and video card. The Altera PCI MegaCore functions were tested on the Stratix EP1S25F1020C5 and EP1S60F1020C6 devices. Hardware testing ensures that the PCI MegaCore functions operate flawlessly under the most stringent conditions. During hardware testing with the Agilent E2928A PCI Bus Exerciser and Analyzer, various tests were performed to guarantee robustness and strict compliance ...
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... Stratix, Stratix GX, and Cyclone device families. This data was obtained by compiling each of the PCI MegaCore functions (parameterized to use one BAR that reserves 1 MByte of memory) in the Stratix EP1S60F1020C6 device. PCI Compiler Version 10.1 (1) f (MHz) I/O Pins MAX 89 > > > > (MHz) I/O Pins MAX 89 > > > > 67 Altera Corporation January 2011 ...
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... The speed and resource utilization estimates are for the supported devices when operating in the PCI Target-Only, PCI Master/Target, and PCI Host-Bridge device modes for each of the application-specific performance settings. 1 Altera Corporation January 2011 shows PCI MegaCore function resource utilization and Logic Elements (LEs) ...
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... The data was obtained by performing compilations on a Stratix II EP2S60F1020C5 device. Each of the device types was parameterized to use one BAR that reserved 1 MByte of memory on the Avalon-MM side. For the PCI Master/Target Peripheral mode, one MByte of memory was reserved on the PCI side. 14 PCI Compiler User Guide ...
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... The data was obtained by performing compilations on a Cyclone II EP2C35F672C7 device. Each of the device types was parameterized to use one BAR that reserved 1 MByte of memory on the Avalon-MM side. For the PCI Master/Target Peripheral mode, one MByte of memory was reserved on the PCI side. Table 10 Stratix GX, and Cyclone devices. Table 10. Memory Utilization & ...
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... The data was obtained by performing compilations on a Cyclone EP1C20F400C7 device. Each of the device types was parameterized to use one BAR that reserved 1 MByte of memory on the Avalon-MM side. For the PCI Master/Target Peripheral mode, one MByte of memory was reserved on the PCI side. Table 11 devices ...
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... Installation and The PCI Compiler is part of the MegaCore IP Library, which is distributed with the Quartus II software and downloadable from the Altera website, Licensing www.altera.com. f For system requirements and installation instructions, refer to Software Installation and Figure 3 User Guide PCI Compiler, where <path> is the installation directory. The default installation directory on Windows is c:\altera\< ...
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... Installation and Licensing Figure 3. Directory Structure <path> Installation directory. ip Contains the Altera MegaCore IP Library and third-party IP cores. altera Contains the Altera MegaCore IP Library. common Contains shared components. ip_toolbench Contains common IP Toolbench files. pci_compiler Contains the PCI Compiler files. const_files Contains constraint files that include all necessary assignments to meet your PCI timing requirements for all supported Altera device families and development kits ...
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... After you purchase a license for PCI Compiler User Guide MegaCore function, you can request a license file from the Altera website at www.altera.com/licensing request a license file, Altera emails you a license.dat file. If you do not have Internet access, contact your local Altera representative. f For more information on OpenCore Plus hardware evaluation, refer to ...
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... Installation and Licensing 20 PCI Compiler User Guide PCI Compiler Version 10.1 Altera Corporation January 2011 ...
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... Verilog HDL and VHDL testbench, and reference designs. This section includes the following chapters: ■ ■ ■ ■ Altera Corporation January 2011 Section I. PCI Compiler With MegaWizard Plug-In Chapter 1, Getting Started Chapter 2, Parameter Settings Chapter 3, Functional Description Chapter 4, Testbench Manager Flow Section I–1 ...
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... PCI Compiler With MegaWizard Plug-In Manager Flow Section I–2 PCI Compiler User Guide PCI Compiler Version 10.1 Altera Corporation January 2011 ...
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... Obtain and install the PCI Compiler. Create a custom variation of a PCI MegaCore function using IP Toolbench Toolbench is a toolbar from which you can quickly and easily view documentation, choose a PCI MegaCore function , specify parameters, and generate all of the files necessary for integrating the parameterized PCI MegaCore function into your design ...
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... PCI MegaCore This walkthrough explains how to create a custom variation of a PCI MegaCore function using the Altera PCI IP Toolbench and the Quartus II Function Design software. When you finish generating a custom variation of the PCI MegaCore function, you can incorporate it into your overall project. ...
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... When you specify a directory that does not already exist, a message asks if the specified directory should be created. Click Yes to create the directory. If you installed the MegaCore IP library in a different directory from where you installed the Quartus II software, add user libraries by following these steps on the New Project Wizard: Add Files page: a ...
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... PCI MegaCore Function Design Walkthrough You have finished creating your new Quartus II project. Launch IP Toolbench To launch IP Toolbench in the Quartus II software, follow these steps 1–4 PCI Compiler User Guide Click Next to close this page and display the New Project Wizard: Family & Device Settings page. ...
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... Click Next to launch IP Toolbench for the PCI Compiler. Click Step 1: Parameterize in IP Toolbench to open the Parameterize - PCI Compiler dialog box. f For more information on the parameters you set during ...
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... Click OK. Click Next to open the Advanced PCI MegaCore Features page. For this walkthrough, use the default settings for all options on this page. Click Finish to complete the parameterization of your pci_mt64 MegaCore function variation. PCI Compiler Version 10.1 Altera Corporation January 2011 ...
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... Step 2: Set Up Simulation An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL model file produced by the Quartus II software. The model allows for fast functional simulation of IP using industry-standard VHDL and Verilog HDL simulators generate an IP functional simulation model for your MegaCore function, follow these steps: 1 ...
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... Pin Planner application, you must explicitly load this file to use Pin Planner. A Verilog HDL or VHDL IP functional simulation model. A tcl script for assigning timing constraints to the MegaCore function. A tcl script for assigning NativeLink simulation testbench settings to the Quartus project. A MegaCore function report file. PCI Compiler Version 10.1 ...
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... To simulate your design, you use the IP functional simulation models generated by IP Toolbench in conjunction with the Altera-provided Design PCI testbench. The IP functional simulation model is the .vo or .vho file generated as specified in files are generated in the directory you specified in the MegaWizard Plug- In Manager. Compile this IP functional simulation model in your simulation environment as instructed below to perform functional simulation of your PCI MegaCore function variation ...
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... Simulating Altera IP in Third-Party Simulation Tools the Quartus II Handbook. 1–10 PCI Compiler User Guide The IP toolbench-generated PCI testbench in the c:\altera\projects\pci_project_nativelink\verilog\pci_mt64 directory The IP functional simulation model generated as specified in 2: Set Up Simulation” on page 1–7 The ModelSim software ® The generated NativeLink script in the project directory, c:\altera\projects On the EDA Tool Option page in the Quartus II software (Tools > ...
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... Open the Quartus II project by double-clicking on pci_top.qpf. 1 This Quartus II project contains a PCI MegaCore function variation with the parameter settings required to simulate the included .vwf files successfully. For a description of the parameter settings required to simulate the included .vwf files, refer to “The Quartus II Simulation Files” on page 1– ...
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... BAR0 reserving 256 Megabytes (MBytes) (memory) BAR1 reserving 64 Bytes (I/O) BAR2 reserving 16 MBytes (memory) BAR3 reserving 1 MByte (memory) BAR4 reserving 64 Kilobytes (KBytes) (memory) BAR5 reserving 4 KBytes (memory) Expansion ROM BAR reserving 1 MByte (memory) PCI Compiler Version 10.1 1–11. Altera Corporation January 2011 ...
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... Latency Timer Expires, 64-Bit PCI, 64-Bit Local mmbw64_lte I/O Write miow Configuration Write mcfgw Altera Corporation January 2011 describes the Quartus II simulation files included in the Description Master Read Master Write PCI Compiler Version 10.1 Getting Started 1–13 PCI Compiler User Guide ...
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... Target Disconnect without Data Response mmbw_tdisc_wod Target Retry Response mmbw_tret Latency Timer Expires mmbw_lte I/O Write miow Configuration Write mcfgw 1–14 PCI Compiler User Guide describes the Quartus II simulation files included in the Description Master Read Master Write PCI Compiler Version 10.1 Altera Corporation January 2011 ...
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... I/O Write tiow Expansion ROM Memory Burst Write, 64-Bit PCI, 64-Bit Local exp_rom_tmbw64 Altera Corporation January 2011 describes the Quartus II simulation files included in the Description Target Read Target Write PCI Compiler Version 10.1 Getting Started 1–15 PCI Compiler User Guide ...
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... For instructions on compiling your design, refer to Quartus II Help. 1–16 PCI Compiler User Guide describes the Quartus II simulation files included in the Description Target Read Target Write Appendix A, Using PCI Constraint File Tcl PCI Compiler Version 10.1 Scripts. Altera Corporation January 2011 ...
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... The constraint file uses the following naming convention: pci_constraints_for_<variation name>.tcl. Monitor the Quartus II Tcl Console to see the actions performed by the script. Choose Start Compilation (Processing menu) in the Quartus II software. After compilation, expand the Timing Analyzer folder in the Compilation Report by clicking the + icon next to the folder name. ...
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... Support following: ■ ■ The PCI Compiler generates PCI constraint files in the form of Tcl scripts that allow you to meet the PCI timing requirements in the Quartus II software. The constraint files use the following naming convention: These constraint files have been tested against PCI Compiler 10.1 and Quartus II 10 ...
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... To source the constraint file, type the following in the Quartus II Tcl console: source pci_constraints_for_<variation name>.tcl add_pci_constraints [-speed "33" | "66"] [-no_compile] [no_pinouts] [-help] describes the directory structure of the pci_mt32 MegaCore <path>/pci_compiler/megawizard_flow /ref_designs/ref_designs/pci_mt32/vhdl PCI Compiler Version 10.1 Getting Started Scripts. 1–19 PCI Compiler User Guide ...
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... SDR SDRAM interface ● SDR SDRAM controller This directory contains a pci_mt32 MegaCore function top- level wrapper file. This wrapper file was generated using IP Toolbench with the following parameters selected using the Parameterize - PCI Compiler Wizard: ● BAR0 reserves 1MB of memory space ● ...
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... Appendix A, Using PCI Constraint File Tcl Compile your project. Master control logic Target control logic DMA engine Data path FIFO buffer functions SDRAM interface describes the directory structure of the pci_mt64 MegaCore PCI Compiler Version 10.1 Getting Started Scripts. 1–21 PCI Compiler User Guide ...
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... SDR SDRAM interface ● SDR SDRAM controller This directory contains a pci_mt64 MegaCore function top- level wrapper file. This wrapper file was generated using IP Toolbench with the following parameters selected using the Parameterize - PCI Compiler Wizard: ● BAR0 reserves 1MB of memory space ● ...
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... Select the appropriate Altera device for your project. Use an Altera-provided PCI constraint file for the device you have selected. f For more information on using PCI constraint files, refer to Appendix A, Using PCI Constraint File Tcl Compile your project. PCI Compiler Version 10.1 Getting Started Scripts. 1–23 PCI Compiler User Guide ...
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... Using the Reference Designs 1–24 PCI Compiler User Guide PCI Compiler Version 10.1 Altera Corporation January 2011 ...
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... PCI configuration space. The wizard is also used to enable and parameterize optional features. For a complete list of parameter names and descriptions found in a generated PCI MegaCore function variation file, refer to Parameters” on page PCI MegaCore The PCI MegaCore functions are capable of operating at clock speeds MHz ...
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... Registers (BARs) You must instantiate at least one BAR in your application design. Multiple BARs must be implemented in sequence starting from BAR0. By default, BAR0 is enabled and reserves 1 MByte of memory space. In addition to allowing normal BAR operation where the system writes the base address value during system initialization, the PCI MegaCore functions allow the base address of any BAR to be hardwired using the Hardwire BAR option ...
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... When CompactPCI technology is selected on the initial page of the wizard, the capabilities list pointer register on the Advanced PCI MegaCore Function Features page is automatically turned on with the default value of 0x40. Altera Corporation January 2011 3–37. PCI Compiler Version 10.1 Parameter Settings “ ...
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... PCI Compiler User Guide 3–28. Allow Variable Byte Enables During Burst Transactions Use in Host Bridge Application Allow Internal Arbitration Logic Disable Master Latency Timer Assume ack64n Response PCI Compiler Version 10.1 “Configuration Registers” on Altera Corporation January 2011 ...
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... I/Os. Turning on Allow Internal Arbitration Logic removes the tri-state buffer from the reqn signal output, allowing the signal to be connected to internal FPGA logic and eliminating the need to use additional device I/O resources or board traces. Altera Corporation January 2011 3–127. PCI Compiler Version 10.1 Parameter Settings “ ...
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... Disabling the master latency timer can also result in increased latency for other master devices in the system. If increased latency for other master devices is unacceptable in your application, this option should not be used. 3–121. PCI Compiler Version 10.1 “64-Bit Single Cycle Memory Altera Corporation January 2011 ...
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... Variation File If you do not want to use the IP Toolbench Parameterize - PCI Compiler wizard, you can specify Altera PCI MegaCore function parameters Parameters directly in the hardware description language (HDL) or graphic design files. Table 2–1. PCI MegaCore Function Parameters (Part Name Format Hexadecimal DEVICE_ID ...
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... Base address register five. H"FF000000" Expansion ROM. This value controls the number of bits in the expansion ROM BAR that are read/write and will be decoded during a memory transaction. PCI Compiler Version 10.1 Description “PCI Base Address 2–2. “PCI Base Address 2–2. “PCI Base Address 2–2. ...
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... To detect base address hits for the expansion ROM, the functions compare the input address to the upper bits of HARDWIRE_EXP_ROM. HARDWIRE_EXP_ROM_ENA must be set to enable expansion ROM support, and the HARDWIRE_EXP_ROM parameter setting defines the number of decoded bits. PCI Compiler Version 10.1 Parameter Settings Description 2–9 ...
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... H"00000000" during a configuration read to CIS when CIS_PTR_ENA is set to 0. H"00000000" Feature enable bits. This parameter is a 32-bit hexadecimal value which controls whether various features are enabled or disabled. The bit definition of this parameter is shown in PCI Compiler Version 10.1 Description Table 2–2. Altera Corporation January 2011 ...
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... EXP_ROM_BAR to set the size and number of bits decoded in the expansion ROM BAR. Otherwise, the expansion ROM BAR is read only and the function returns H"0000000" when the expansion ROM BAR is read. PCI Compiler Version 10.1 Parameter Settings Description CC Definition 2–11 ...
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... If this bit is set to 1, the tri-state buffer on the reqn signal is removed, allowing an arbiter to be implemented without using device pins for the reqn and gntn signals. PCI Compiler Version 10.1 Definition Altera Corporation January 2011 ...
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... If starting a new design, Altera recommends adding the data steering logic in the local side application for lower logic utilization and better overall performance. PCI Compiler Version 10.1 ...
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... If this bit is set to 1, the latency timer circuitry is disabled. In this case, the or pci_mt32 ownership normally when the local side signal lm_lastn is asserted or when the target terminates the PCI transaction with a retry, disconnect, or abort. 0 64-bit only PCI devices ...
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... Reserved Note to Table 2–2: (1) These parameters affect master functionality and therefore only affect the pci_mt64 and pci_mt32 MegaCore functions. Altera Corporation January 2011 Default Value standard master burst transaction the byte enables accompanying the initial data word provided by the local side are used throughout the master burst transaction ...
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... Variation File Parameters 2–16 PCI Compiler User Guide PCI Compiler Version 10.1 Altera Corporation January 2011 ...
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... Local target control—controls local-side interface operation in target mode Local master control—controls the local side interface operation in master mode (pci_mt64 and pci_mt32 MegaCore functions only) Local address/data/command/byte enables—multiplexes and registers all address, data, command, and byte-enable signals to the local side interface. PCI Compiler Version 10.1 ...
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... Byte Enable Control Local Target Control PCI Compiler Version 10.1 cmd_reg[6..0] stat_reg[6..0] cache[7..0] lm_req32n lm_req64n lm_lastn lm_rdyn lm_ackn lm_adr_ackn lm_dxfrn lm_tsr[9..0] l_adi[63..0] l_cbeni[7..0] l_dato[63..0] l_adro[63..0] l_beno[7..0] l_cmdo[3..0] l_ldat_ackn l_hdat_ackn lt_rdyn lt_discn lt_abortn lirqn lt_framen lt_ackn lt_dxfrn lt_tsr[11..0] Altera Corporation January 2011 ...
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... Altera Corporation January 2011 pci_mt32 Parameterized Configuration Registers Local Master Control Control Local Address/ Data/Command/ Byte Enable Control Local Target Control PCI Compiler Version 10.1 Functional Description cmd_reg[6..0] stat_reg[6..0] cache[7..0] lm_req32n lm_lastn lm_rdyn lm_ackn lm_adr_ackn lm_dxfrn lm_tsr[9..0] l_adi[31..0] l_cbeni[3..0] l_dato[31..0] l_adro[31..0] l_beno[3..0] l_cmdo[3 ...
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... PCI Compiler User Guide pci_t64 Parameterized Configuration Registers Local Address/ Data/Command/ Byte Enable Control Local Target Control PCI Compiler Version 10.1 cmd_reg[6..0] stat_reg[6..0] l_adi[63..0] l_dato[63..0] l_adro[63..0] l_beno[7..0] l_cmdo[3..0] l_ldat_ackn l_hdat_ackn lt_rdyn lt_discn lt_abortn lirqn lt_framen lt_ackn lt_dxfrn lt_tsr[11..0] Altera Corporation January 2011 ...
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... Generator serrn Altera Corporation January 2011 pci_t32 Parameterized Configuration Registers Local Address/ Data/Command/ Byte Enable Control Local Target Control PCI Compiler Version 10.1 Functional Description cmd_reg[6..0] stat_reg[6..0] l_adi[31..0] l_dato[31..0] l_adro[31..0] l_beno[3..0] l_cmdo[3..0] lt_rdyn lt_discn lt_abortn lirqn lt_framen lt_ackn lt_dxfrn lt_tsr[11..0] ...
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... The PCI MegaCore function has decoded a valid address for one of its BARs and it accepts the transactions (assert devseln) The PCI MegaCore function is ready for the data transfer (assert trdyn) PCI Compiler Version 10.1 Error perrn Reporting serrn Signals Interrupt intan Request Signal Altera Corporation January 2011 ...
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... Transaction Terminations” on page 3–77 devseln trdyn Don’t care De-Assert Assert De-assert De-assert Assert De-assert Assert PCI Compiler Version 10.1 Functional Description stopn irdyn Don’t care Don’t care Assert Don’t care Assert Assert Assert Don’t care Assert Don’ ...
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... During data phases, data is driven over the ad[63..0] bus and byte enables are driven over the cben[7..0] bus. Additionally, parity for ad[63..32] and cben[7..4] is presented over the par64n signal. PCI Compiler Version 10.1 Altera Corporation January 2011 ...
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... Figure 3–6. Master Device Signals A 32-bit master sequence begins when the local side asserts lm_reqn32n to request mastership of the PCI bus. The PCI MegaCore function then asserts reqn to request ownership of the PCI bus. After receiving gntn from the PCI bus arbiter and after the bus idle state is detected, the function initiates the address phase by asserting framen, driving the PCI address on ad[31 ...
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... The master device should stop the current transaction The master device should abort the current transaction shows the possible control signal combinations on the PCI bus “Master Mode Operation” on page 3–134 PCI Compiler Version 10.1 for more for more information Altera Corporation January 2011 ...
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... Open-drain—Signal that is shared by multiple devices as a wire-OR. The signaling agent asserts the open-drain signal, and a weak pull- up resistor deasserts the open-drain signal. The pull-up resistor may require two or three PCI bus clock cycles to restore the open-drain signal to its inactive state ...
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... For and pci_mt32 implemented. – Command/byte enable. The multiplexed command/byte enable bus. During the address phase, this bus indicates the command. During the data phase, this bus indicates byte enables. For only is implemented. cben[3..0] – ...
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... PCI Compiler Version 10.1 Functional Description Description req64n signal is an output from req64n has the same timing pci_mt32 signal is an output from a bus master ...
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... The PCI MegaCore functions assert only when the local side asserts the intan the bit (bit 10 of the command register int_dis PCI Compiler Version 10.1 Description signal is an active-low interrupt to the signal and lirqn Altera Corporation January 2011 ...
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... Memory write and invalidate enable. Bit 4 of the command register. Parity error response enable. Command register bit 6. System error response enable. Command register bit 8. (1) Interrupt disable. Command register bit 10. PCI Compiler Version 10.1 Functional Description Description cache[7..0] bus is bus drives cmd_reg[6..0] Table 3– ...
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... Master abort received. Status register bit 13. Signaled system error. Status register bit 14. Parity error detected. Status register bit 15. Interrupt status. Status register bit 3. (1) summarizes the PCI local interface signals for the address, data, PCI Compiler Version 10.1 Description Altera Corporation January 2011 ...
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... Altera Corporation January 2011 Description Local address/data input. This bus is a local-side time multiplexed address/data bus. This bus changes operation depending on the function you are using and the type of transaction. During master transactions, the local side must provide the address ...
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... PCI Compiler User Guide Description Local address output. The l_adro[63..0] bus is driven by the PCI MegaCore functions during target transactions. The pci_mt32 and pci_t32 functions only implement l_adro[31..0]. During dual address transactions in the pci_mt64 and pci_t64 MegaCore functions, the l_adro[63 ...
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... PCI side. If the address of the DWORD transaction is not a QWORD boundary, and is asserted. l_hdat_ackn This signal is not implemented in the functions. PCI Compiler Version 10.1 Functional Description bus is driven by the PCI l_adro[31..0] bus. The output is used is being DWORD bus, i.e., when l_ldat_ackn boundary QWORD ...
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... PCI Bus Signals Target Local-Side Signals Table 3–7 interface between the PCI MegaCore function and the local-side peripheral device(s) during target transactions. 1 Table 3–7. Target Signals Connecting to the Local Side (Part Name Type Input lt_abortn Input lt_discn 3–20 PCI Compiler User Guide ...
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... PCI bus master inserts wait states. Low Local target data transfer. The PCI MegaCore function asserts the lt_dxfrn signal when a data transfer on the local side is successful during a target transaction. PCI Compiler Version 10.1 Functional Description Description lt_rdyn to indicate lt_rdyn inserts wait states lt_rdyn trdyn in the first data ...
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... Local target transaction status register. The bus carries several signals which can be monitored for the transaction status. Refer to Low Local interrupt request. The local-side peripheral device asserts to signal a PCI bus interrupt. Asserting this lirqn signal forces the PCI MegaCore function to assert the ...
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... PCI transfer. This signal is asserted to indicate that there was a successful data transfer on the PCI side during the previous clock cycle. Dual address cycle. When asserted, this signal indicates that the current transaction is using a dual address cycle. PCI Compiler Version 10.1 Functional Description indicates bar_hit[5..0] is used for ). BAR0 ...
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... When a local side transaction is not in progress, local side inputs should be deasserted. Low Local master request 32-bit data transaction. The local side asserts this signal to request ownership of the PCI bus for a 32-bit master transaction. To request a master transaction sufficient for the local-side device to assert requesting a 32-bit transaction, only write transaction or l_dato[31 ...
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... Local master transaction status register bus. These signals inform the local interface of the transaction’s progress. Refer to for a detailed description of the bits in this bus. PCI Compiler Version 10.1 Functional Description Description lm_rdyn signal to lm_rdyn ...
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... PCI bus), but then deassert gntn (before the pci_mt64 or pci_mt32 have asserted framen) to give mastership of the bus to a higher priority device. In systems where this situation may occur, the local side logic should hold the address and command on the l_adi[63..0] and l_cbeni[7..0] buses until the adr_phase bit is asserted (lm_tsr[2]) to ensure that the pci_mt64 or pci_mt32 function has assumed mastership of the bus and that the current address and command bits have been transferred ...
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... The memory read multiple and memory read line commands are treated as memory reads. The memory write and invalidate command is treated as a memory write. The local side sees the exact command on the l_cmdo[3..0] bus ...
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... SIG) PCI Local Bus Specification, Revision 3.0 and the Compliance Checklist, Revision 3.0. These specifications define two header formats, type one and type zero. Header type one is used for PCI-to-PCI bridges; header type zero is used for all other devices, including the Altera PCI MegaCore functions. 3–28 PCI Compiler User Guide PCI Compiler Version 10 ...
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... Read/write refers to the status at run time, i.e., from the perspective of other PCI bus agents. You can set some of the read-only registers when creating a custom PCI design by using the IP Toolbench Parameterize - PCI Compiler wizard. For example, you can change the Altera Corporation January 2011 shows the defined 64-byte configuration space ...
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... Base address register one Base address register two Base address register three Base address register four Base address register five CardBus CIS pointer Subsystem vendor ID Subsystem ID Expansion ROM BAR Capabilities pointer Interrupt line Interrupt pin Minimum grant (1) (1) Maximum latency Altera Corporation January 2011 ...
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... ID register through the wizard. Refer to Table 3–15. Device ID Register Format Altera Corporation January 2011 Table 3–14. Data Bit Mnemonic 15..0 ven_id Data Bit Mnemonic 15..0 dev_id PCI Compiler Version 10.1 Functional Description Read/Write Definition Read PCI vendor ID Table 3–15. Read/Write Definition Read Device ID 3–31 ...
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... Memory access enable. When high, respond to the PCI bus memory accesses as a target. Master enable. When high, mstr_ena mastership of the PCI bus. Bit 2 is hardwired to host bridge options are enabled through the wizard. – Memory write and invalidate enable. This bit controls whether the master may generate a MWI command ...
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... MHz. The PCI MegaCore functions can function at either 66 MHz or 33 MHz depending on the device used. You can set this bit turning on PCI 66MHz Capable on the initial page of the IP Toolbench Parameterize - PCI Compiler wizard. – Reserved. Read/write Reported data parity. When high, ...
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... Table 3–18. Revision ID Register Format 3–34 PCI Compiler User Guide Read/Write Read/write Signaled target abort. This bit is set when a local peripheral device terminates a transaction. The function automatically sets this bit if it issued a target abort after the local side asserted lt_abortn the [1] output ...
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... This read/write register is written by system software at power-up. The value in this register is driven to the local side on the cache[7..0] bus. The local side must use this value when using the memory read line, memory read multiple, and memory write and invalidate commands in master mode. Refer to 1 Table 3– ...
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... The latency timer register is an 8-bit register with bits 2, 1, and 0 tied to ground. The register defines the maximum amount of time, in PCI bus clock cycles, that the PCI function can retain ownership of the PCI bus. After initiating a transaction, the function decrements its latency timer by one on the rising edge of each clock cycle ...
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... Marks the reserved memory as prefetchable or non-prefetchable Size of memory or I/O address space reserved for the BAR When compiling the PCI function, the Quartus II software generates informational messages informing you of the number and options of the BARs you have specified. PCI Compiler Version 10.1 Functional Description 3–37 ...
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... Memory prefetchable. The pre_fetch of memory are prefetchable by the host bridge. Base address registers. PCI Compiler Version 10.1 bit indicates whether the blocks Altera Corporation January 2011 ...
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... Base address registers. When implementing a hardwire BAR, the corresponding BARs become read-only. A configuration write to the hardwired BAR will proceed normally. However, a configuration read of hardwired BARs will return the value set in the hardwire BARn parameter. PCI Compiler Version 10.1 Functional Description Table 3–24. 3–39 ...
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... CIS pointer register is pointing to an expansion ROM space. Data Bit Mnemonic Read/Write 15..0 sub_ven_id PCI Compiler Version 10.1 shows this register’s format. For Definition Table 3–26. The default Definition Read PCI subsystem/vendor ID Altera Corporation January 2011 ...
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... ROM address space by setting this bit to 0. You can enable the address decoding of the expansion ROM by setting this bit to 1. – Expansion ROM base address registers. PCI Compiler Version 10.1 Functional Description Definition Read PCI subsystem ID Definition bit indicates whether or not the ...
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... When implementing a hardwire expansion ROM BAR, the corresponding BARs become read only. However, bit 0 is read/write, allowing you to disable the expansion ROM BAR after power-up. 3–29. Data Bit Mnemonic Read/Write Read/write cap_ptr PCI Compiler Version 10.1 Definition Capabilities pointer register Altera Corporation January 2011 ...
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... Minimum Grant Register The minimum grant register is an 8-bit read-only register that defines the length of time the function would like to retain mastership of the PCI bus. The value set in this register indicates the required burst period length in 250-ns increments. You can set this register through the wizard. Refer to Table Table 3– ...
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... Data Bit Mnemonic 7..0 max_lat Table 3–34 lists the PCI and local side signals that apply for pci_t64 PCI Signals ad[31..0] v cben[3.. PCI Compiler Version 10.1 Read/Write Definition Read Maximum latency register pci_mt32 pci_t32 ad[31..0] cben[3.. Altera Corporation January 2011 ...
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... Altera Corporation January 2011 pci_t64 Local-Side Datapath Signals v l_adi[31..0] l_cbeni[3..0] v l_adro[31..0] v l_dato[31..0] v l_beno[3.. Target Local-Side Control Signals Master Local-Side Control Signals PCI Compiler Version 10.1 Functional Description pci_mt32 pci_t32 l_adi[31..0] l_adro[31..0] l_dato[31..0] l_beno[3.. 3– ...
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... A read or write transaction begins after a master device acquires mastership of the PCI bus and asserts framen to indicate the beginning of a bus transaction. If the transaction is a 64-bit transaction, the master device asserts the req64n signal at the same time as it asserts the framen signal ...
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... January 2011 “Target Transaction Terminations” on page 3–77 The PCI MegaCore function treats the memory read line and memory read multiple commands as memory read. Similarly, the function treats the memory write and invalidate command as a memory write. The local-side application must implement any special requirements for these commands ...
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... If the address of the transaction matches the memory range specified in a base address register, the PCI MegaCore function turns on the drivers for the ad bus, devseln, trdyn, stopn, and par (as well as par64 and ack64n for 64-bit transactions) in the following clock cycle. PCI Compiler Version 10.1 Altera Corporation January 2011 ...
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... January 2011 The PCI MegaCore function drives and asserts devseln (and ack64n for 64-bit transactions) to indicate to the master device that it is accepting the transaction. One or more data phases follow, depending on the type of read transaction. PCI Compiler Version 10.1 Functional Description 3–49 ...
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... This signal is not applicable to the pci_mt32 or pci_t32 MegaCore functions. 3–50 PCI Compiler User Guide shows the waveform for a 64-bit single-cycle memory read Adr BE0_L BE0_H Adr-PAR Z Adr D0_L D0_H 000 181 PCI Compiler Version 10 D0_L D0_H D0-L-PAR D0-H-PAR 6 BE0_L BE0_H 581 000 Altera Corporation January 2011 ...
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... The PCI MegaCore function registers the data into its internal pipeline on the rising edge of clock cycle 7. The local side transfer is indicated by the signal is low during the clock cycle where a data transfer on the local side occurs. ...
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... PCI Compiler Version 10.1 , and ack64n to end the high during this clock cycle. bus because the cycle is complete. ad framen lt_framen , and Altera Corporation January 2011 is ...
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... Altera Corporation January 2011 Figure 3–8 illustrates a burst memory read target Figure 3– 64-bit zero-wait state burst Figure 3–8 PCI Compiler Version 10.1 Functional Description shows the lt_tsr[9] signal 3–53 ...
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... D0-H-PAR D0_L D1_L D0_H D1_H 381 PCI Compiler Version 10 D1_L D2_L D3_L D1_H D2_H D3_H BE1_L BE2_L BE3_L BE2_H BE1_H BE3_H D0-L-PAR D1-L-PAR D2-L-PAR D3-L-PAR D1-H-PAR D2-H-PAR D3-H-PAR Adr 6 D2_L D3_L D4_L D2_H D3_H D4_H 781 000 Altera Corporation January 2011 13 ...
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... PCI MegaCore function deasserts lt_ackn, and as a result lt_dxfrn is also deasserted. This situation prevents further data from being transferred on the local side because the internal pipeline of the PCI MegaCore function is full. The 64-bit extension signals shown in pci_mt32 and pci_t32 MegaCore functions. ...
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... BE0_H Z D0-H-PAR D0_L D0_H 381 PCI Compiler Version 10.1 Figure 3–8 with the D1_L D2_L D1_H D2_H Z BE2_L BE1_L BE1_H BE2_H D0-L-PAR D1-L-PAR D2-L-PAR D1-H-PAR D2-H-PAR Adr 6 D1_L D2_L D3_L D1_H D2_H D3_H 781 381 781 Altera Corporation January 2011 13 000 ...
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... Mismatched Bus Width Memory Read Target Transactions The following description applies only to the pci_mt64 and pci_t64 MegaCore functions handling mismatched bus width memory read target transactions. When using the pci_mt64 or pci_t64 MegaCore functions to accept 32-bit memory read transactions, the local side data bus width is 64 bits while the PCI data bus width is 32 bits ...
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... The pci_mt64 and the pci_t64 functions always transfer 64-bit data on the local side 32-bit single-cycle memory read transaction, only one DWORD is transferred to the PCI master BE0_L Adr-PAR Z D0_L D0_H 101 PCI Compiler Version 10 D0_L D0-L-PAR Adr 6 BE0_L BE0_L BE0_H BE0_H 501 000 Altera Corporation January 2011 ...
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... Altera Corporation January 2011 shows a 32-bit PCI side and 64-bit local side burst memory Figure 3–12 are the same as those shown in Figure 3–12 at clock cycle 7. PCI Compiler Version 10.1 Functional Description Figure 3–8, takes one clock cycle on Figure 3–12, lt_tsr[7] is not 3–59 ...
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... The value on ad[31..0] is not a QWORD address boundary (ad[2..0] == B”100”). 3–60 PCI Compiler User Guide BE0_H BE0_H Z D0_L D1_L D0_H D1_H BE0_H 301 PCI Compiler Version 10 D0_H D1_H D1_H D1_L BE2_H BE2_H BE1_L D1-L-PAR D1-H-PAR D0-H-PAR Adr 6 D2_L D2_H BE1_L BE1_H 701 000 Altera Corporation January 2011 13 ...
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... I/O transactions. Refer to the PCI Local Bus Specification, Revision 3.0 for more information on handling invalid combinations of these signals BE0_L Z Adr-PAR D0_L 102 PCI Compiler Version 10.1 Functional Description Figure 3–13 shows D0_L D0-L-PAR Adr 2 BE0_L 502 000 3–61 ...
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... PCI MegaCore functions assert trdyn independent from the lt_rdyn signal The local side cannot retry, disconnect, or abort configuration cycles BE0_L Adr-PAR Z 100 PCI Compiler Version 10.1 Figure 3–14. The configuration read D0_L D0-L-PAR 500 000 Altera Corporation January 2011 ...
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... The PCI MegaCore function drives and asserts devseln (and ack64n for 64-bit transactions) to indicate to the master device that it is accepting the transaction. One or more data phases follow, depending on the type of write transaction. PCI Compiler Version 10.1 Functional Description 3–63 ...
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... This signal is not applicable to the pci_mt32 or pci_t32 MegaCore functions. 3–64 PCI Compiler User Guide shows the waveform for a 64-bit single-cycle memory write D0_L D0_H 7 BE0_L BE0_H Adr-PAR D0-L-PAR D0-H-PAR Adr 7 BE0_L BE0_H 181 PCI Compiler Version 10 D0_L D0_H 581 000 Altera Corporation January 2011 ...
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... PCI MegaCore (Figure 3–15), the PCI MegaCore function delays the assertion of to inform the PCI master that it is ready to accept data. trdyn PCI Compiler Version 10.1 Functional Description framen that corresponds to the l_cmdo[3..0] and address , ...
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... The PCI MegaCore function resets all 8 completed the transaction. The PCI MegaCore function also tri-states its control signals. The PCI MegaCore function deasserts 9 data is in the internal pipeline. 3–66 PCI Compiler User Guide Event cben bus, and drives the byte enables on the ...
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... Altera Corporation January 2011 shows a 64-bit zero-wait state burst memory write target PCI Compiler Version 10.1 Functional Description Figure 3–16 3–67 ...
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... D1_H BE1_L BE0_L BE1_H BE0_H 381 PCI Compiler Version 10 D3_L D4_L D3_H D4_H BE3_L BE4_L BE3_H BE4_H D2-L-PAR D3-L-PAR D4-L-PAR D2-H-PAR D3-H-PAR D4-H-PAR D2_L D3_L D4_L D2_H D3_H D4_H BE2_L BE3_L BE4_L BE2_H BE3_H BE4_H 781 000 Altera Corporation January 2011 14 ...
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... MegaCore function deasserts lt_ackn and as a result lt_dxfrn is also deasserted. This prevents data from being transferred to the local side in clock cycle 8 because the internal pipeline of the function does not have valid data. Figure 3–17. Burst Memory Write Target Transaction with PCI Master Wait State ...
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... D1_L D0_H D1_H BE1_L BE0_L BE1_H BE0_H 381 781 PCI Compiler Version 10.1 Figure 3–16 with the local D3_L D3_H BE3_L BE3_H D2-L-PAR D3-L-PAR D2-H-PAR D3-H-PAR D2_L D3_L D2_H D3_H BE2_L BE3_L BE2_H BE3_H 381 781 000 Altera Corporation January 2011 14 ...
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... Mismatched Bus-Width Memory Write Target Transactions The following description applies only to the pci_mt64 and pci_t64 functions handling mismatched bus width memory write target transactions. When using the pci_mt64 or pci_t64 MegaCore functions to accept 32-bit memory write transactions, the local side data bus width is 64 bits while the PCI data bus width is 32 bits ...
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... Note to Figure 3–19: (1) Ignore this signal for this transaction. 3–72 PCI Compiler User Guide 3–19, the local-side transfer occurs in clock cycle 7 because D0_L BE0_L Adr-PAR D0-L-PAR Adr Adr 7 101 PCI Compiler Version 10 D0_L BE0_L 000 501 Altera Corporation January 2011 11 ...
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... Figure 3–17. The main difference between the two figures is Figure 3–20 l_ldat_ackn and l_hdat_ackn toggle to indicate only applies to the pci_mt64 and pci_t64 functions. For PCI Compiler Version 10.1 Functional Description Figure 3–20, the high DWORD is Figure 3–17 reflects the 3–73 ...
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... PCI Compiler User Guide D2_L D0_L D1_L BE2_L BE0_L BE1_L D0-L-PAR D1-L-PAR Adr 7 D0_L D1_L BE0_L BE1_L 301 PCI Compiler Version 10 D3_L D4_L BE3_L BE4_L D2-L-PAR D3-L-PAR D4-L-PAR D2_L D3_L D4_L BE2_L BE3_L BE4_L 701 000 Altera Corporation January 2011 14 ...
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... I/O transactions. Refer to the PCI Local Bus Specification, Revision 3.0 for more information on handling invalid combinations of these signals D0_L BE0_L Adr-PAR D0-L-PAR Adr 3 BE0_L 102 PCI Compiler Version 10.1 Functional Description Figure 3–21 shows D0_L 502 000 3–75 ...
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... Because the configuration write does not require local side actions, the PCI MegaCore function asserts trdyn independent from the lt_rdyn signal The local side cannot retry, disconnect, or abort configuration cycles D0_L BE0_L Adr-PAR D0-L-PAR 100 PCI Compiler Version 10 500 000 Altera Corporation January 2011 11 ...
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... PCI MegaCore function. MegaCore functions, excluding the 64-bit signals as noted for pci_mt32 and pci_t32. Altera Corporation January 2011 PCI Compiler Version 10.1 Functional Description Figure 3–23 applies to all PCI 3–77 ...
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... This signal is not applicable to either the pci_mt32 or pci_t32 MegaCore functions. 3–78 PCI Compiler User Guide Adr D0_L D0_H 7 BE0_L BE0_H Adr-PAR D0-L-PAR D0-H-PAR PCI Compiler Version 10 D1-L D1_H BE1_L BE1_H D1-L-PAR D1-H_PAR Adr 7 BE0_L BE0_H 381 000 Altera Corporation January 2011 ...
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... In this case, the local-side device must request a disconnect. The local-side device must keep track of the current data transfer address; if the transfer exceeds its address range, the local side should request a disconnect by asserting lt_discn. PCI Compiler Version 10.1 Functional Description data. 3–79 ...
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... PCI MegaCore functions, excluding the 64-bit Adr D0_L D0_H 7 BE0_L BE0_H Adr-PAR D0-L-PAR D0-H-PAR Adr 7 BE0_L BE0_H 000 381 PCI Compiler Version 10.1 Figure 3– D1-L D1_H BE1_L BE1_H D1-L-PAR D1-H_PAR D0_L D0_H 781 381 000 Altera Corporation January 2011 ...
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... Figure 3–25 transaction where multiple data phases are completed. applies to all PCI MegaCore functions, excluding the 64-bit extension signals as noted for pci_mt32 and pci_t32. One additional data phase will be completed on the local side following the assertion of lt_discn. Figure 3–25. Disconnect in a Burst Write Transaction ...
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... This signal is not applicable to either the pci_mt32 or pci_t32 MegaCore functions. 3–82 PCI Compiler User Guide shows an example of a disconnect during a burst read 3–26, lt_rdyn is asserted in clock cycle 5 and lt_discn BE0_L BE0_H Adr-PAR Z D0_L D0_H 381 PCI Compiler Version 10 D0_L D0_H D0-L-PAR D0-H-PAR Adr 6 781 381 000 Altera Corporation January 2011 11 ...
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... Altera Corporation January 2011 shows an example of a disconnect during a burst target read D0_L D1_L Z D0_H D1_H BE0_L BE1_L BE1_H BE0_H Z D0-L-PAR D0-H-PAR D0_L D1_L D0_H D1_H 381 PCI Compiler Version 10.1 Functional Description D1-L-PAR D1-H-PAR Adr 6 781 381 000 13 3–83 ...
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... PCI Compiler User Guide shows an example of a disconnect during a 32-bit read BE0_L BE0_H Adr-PAR Z D0_L D0_H 101 PCI Compiler Version 10 D0_L D0_H D0-L-PAR D0-H-PAR Adr 6 BE0_L BE0_H 501 000 Altera Corporation January 2011 ...
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... Altera Corporation January 2011 shows an example of a disconnect during a 32-bit read BE0_L BE0_H Z Adr-PAR Adr D0_L D0_H 101 PCI Compiler Version 10.1 Functional Description D0_L D0_H D0-L-PAR D0-H-PAR 6 BE0_L BE0_H 501 000 3–85 ...
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... This condition most commonly occurs during I/O transactions. The local-side device must ensure that this requirement is met, and if it receives this type of transaction, it must assert lt_abortn to request a target abort termination. PCI Compiler Version 10.1 “Status Register” shows the PCI MegaCore Altera Corporation January 2011 ...
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... D0_L D1-L D0_H D1_H BE0_L BE1_L BE1_H BE0_H D0-L-PAR D1-L-PAR D0-H-PAR D1-H_PAR Adr D0_L D0_H BE0_L BE0_H 381 PCI Compiler Version 10.1 Functional Description D2_L D3_L D2_H D3_H BE2_L BE3_L BE2_H BE3_H D2-L-PAR D3-L-PAR D2-H_PAR D3-H_PAR 7 D1-L D2_L D1_H D2_H ...
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... Asserting wait states on the last data phase of a PCI write transaction can cause a data loss if another PCI transaction begins during the wait states. This is because the PCI MegaCore function has only one register pipeline phase that is used to register the PCI data. To prevent data loss, the local side design should load the data into a holding register if a wait state is needed on the last data phase ...
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... Altera Corporation January 2011 Table 3–37 lists the PCI and local side signals that apply for each Signal Name pci_mt64 PCI Signals Local-side Data Path Signals PCI Compiler Version 10.1 Functional Description pci_mt32 ad[31..0] cben[3.. l_adi[31..0] l_cbeni[3..0] l_adro[31..0] l_dato[31..0] l_beno[3..0] v 3–89 ...
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... Assume ack64n Response option is turned on in the Parameterize - PCI Compiler wizard. For more information on the Assume ack64n Response option, refer to “Assume ack64n Response” on page PCI Compiler Version 10.1 pci_mt32 2–6. Altera Corporation January 2011 ...
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... The PCI function asserts the reqn signal to the PCI bus arbiter to request bus ownership. When the PCI bus arbiter grants the PCI function bus ownership by asserting the gntn signal, the local side is alerted and must provide the address and command ...
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... systems where this situation may occur, the local-side logic should hold the address and command on the l_adi[31..0] and l_cbeni[3..0] buses until the address phase bit (i.e., lm_tsr[2]) is asserted to ensure that the pci_mt64 or pci_mt32 function has assumed mastership of the bus and that the current address and command have been transferred. 3–92 ...
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... The local side asserts lm_req32n to request a 32-bit transaction (or lm_req64n to request a 64-bit transaction.) Consequently, the PCI side asserts reqn to request bus ownership from the PCI arbiter. When the PCI arbiter grants bus ownership by asserting the gntn signal, the PCI side asserts lm_adr_ackn on the local side to acknowledge the transaction address and command ...
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... Master Mode Operation 4. 5. The pci_mt64 and pci_mt32 functions treat memory read, memory read multiple, and memory read line commands in the same way. Any additional requirements for the memory read multiple and memory read line commands must be implemented by the local-side application. 3–94 ...
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... Adr Z D0_L 0 Z D0_H Adr-PAR Z Z Adr 6 BE_L BE_H 002 004 008 208 PCI Compiler Version 10.1 Functional Description D1_L D2_L Z D1_H D2_H Z Z BE_L Z BE_H D0-H-PAR D1-H-PAR D2-H-PAR D0-H-PAR D1-H-PAR D2-H-PAR D0_L D1_L D2_L D0_H D1_H D2_H ...
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... Event to request a 64-bit transaction. lm_req64n to the PCI bus arbiter to request bus ownership. At the same time, the [0] to indicate to the local side that the master is requesting the PCI bus. to grant the PCI bus to the function. Although gntn ...
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... PCI side on the signal is asserted. Because lm_tsr [8] in the same clock cycle to inform the local side that a PCI Compiler Version 10.1 Functional Description lm_rdyn signal is asserted on to inform the local side that data is asserted in the current ...
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... PCI Compiler Version 10.1 framen , informing the local side that the function lm_ackn . The assertion of the lm_dxfrn are deasserted, indicating that the current , informing the local side that the function lm_ackn . The assertion of the lm_dxfrn l_dato Altera Corporation January 2011 bus ...
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... Altera Corporation January 2011 shows the same transaction Adr Z D0_L 0 6 BE_L Adr-PAR Z Adr BE_L 6 002 004 008 PCI Compiler Version 10.1 Functional Description Figure 3–31, but the local D1_L D2_L Z Z D0-L-PAR D1-L-PAR D2-L-PAR D0_L D1_L D2_L 108 000 3–99 ...
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... PCI Compiler Version 10.1 Figure 3–31 with the local D1_L D2_L Z D1_H D2_H Z Z BE_L Z BE_H D0-L-PAR D1-L-PAR D2-L-PAR D0-H-PAR D1-H-PAR D2-H-PAR D0_L D1_L D2_L D0_H D1_H D2_H 308 208 308 200 000 Altera Corporation January 2011 ...
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... Data transfer is suspended on the PCI side in clock cycle 9 and on the local side in clock cycle 10. Altera Corporation January 2011 shows the same transaction as in PCI Compiler Version 10.1 Functional Description Figure 3–31 with the PCI 3–101 ...
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... D1_L 0 Z D0_H D1_H 0 6 BE_L 0 BE_H Adr-PAR Z D0-L-PAR Z D0-H-PAR Adr 6 BE_L BE_H D0_L D0_H 002 004 008 208 308 PCI Compiler Version 10 D2_L Z D2_H D1-L-PAR D2-L-PAR D1-H-PAR D2-H-PAR D1_L D2_L D1_H D2_H 208 308 200 000 Altera Corporation January 2011 ...
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... However, if your application is a system that has 32-bit and 64-bit PCI devices and the local side wants to transfer one 64-bit data word, Altera recommends that you perform a 32-bit burst memory read transaction. PCI Compiler Version 10.1 Functional Description Figure 3–31 with just one 3–103 ...
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... For pci_mt32, lm_req32n should be substituted for lm_req64n for 32-bit master transactions. 3–104 PCI Compiler User Guide Adr Z D0_L 0 Z D0_H 0 6 BE_L 0 BE_H Z Adr-PAR Z Adr BE_L 6 BE_H 002 004 008 208 PCI Compiler Version 10 D0-L-PAR D0-H-PAR D0_L D0_H 308 200 000 Altera Corporation January 2011 ...
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... Figure 3–36 3–35, except that in Figure 3– Adr 0 6 Adr-PAR Adr BE_L 6 001 002 004 PCI Compiler Version 10.1 Functional Description is the same as shown in the local side master interface D0_L Z BE_L Z Z D0-L-PAR D0_L 008 108 000 3–105 ...
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... Master Mode Operation Mismatched Bus Width Burst Memory Read Master Transactions The following description applies only to the pci_mt64 MegaCore functions handling mismatched bus width memory read master transactions. Figure 3–37 master transaction. The events shown in shown in requests a 64-bit transaction by asserting lm_req64n. The pci_mt64 function asserts req64n on the PCI side ...
Page 181
... Altera Corporation January 2011 Adr Z D0_L Adr-PAR Adr BE_L 6 BE_H 002 004 008 Figure PCI Compiler Version 10.1 Functional Description D1_L D2_L D3_L Z BE_L Z D0-L-PAR D1-L-PAR D2-L-PAR D3-L-PAR D0_L D1_L D2_L D3_L 108 000 3–36. This figure applies to both 3–107 ...
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... MegaCore function. The local side asserts lm_req32n (and lm_req64n in the case of a 64-bit transaction) to request a transaction. Consequently, the PCI side asserts reqn to request mastership of the bus from the PCI arbiter. When the PCI bus arbiter grants mastership by asserting the gntn signal, the local side asserts lm_adr_ackn to acknowledge the transaction’ ...
Page 183
... PCI target, the PCI target asserts devseln to claim the transaction. One or more data phases follow next, depending on the type of write transaction. PCI Compiler Version 10.1 Functional Description “Allow Variable Byte Enables During for more information about this 3–109 ...
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... D0-L-PAR D0-H-PAR Adr D0_L D1_L D0_H D1_H 7 BE_L BE_H 002 004 008 208 PCI Compiler Version 10 D2_L D3_L Z D1_L D1_H D2_H D3_H Z Z BE_L Z BE_H D1-L-PAR D2-L-PAR D3-L-PAR D2-H-PAR D3-H-PAR D1-H-PAR D2_L D3_L D3_H D2_H 308 000 Altera Corporation January 2011 ...
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... Event to request a 64-bit transaction. lm_req64n to the PCI bus arbiter to request bus ownership. At the same time, the to indicate to the local side that the master is requesting control of the to grant the PCI bus to the function. Although gntn ...
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... Because the lm_tsr[9 ...
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... These actions indicate that the transaction has ended and there trdyn , informing the local side that a successful data transfer lm_tsr[8] , informing the local side that the data transfer mode is lm_tsr[3] PCI Compiler Version 10.1 Functional Description is asserted in the current lm_ackn lm_dxfrn , l_ldat_ackn , and ...
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... Adr D0_L 0 7 Adr-PAR Adr D0_L D1_L 7 BE_L 001 002 004 008 MegaCore function. pci_mt32 PCI Compiler Version 10.1 Figure 3–42, but the local D1_L D2_L Z Z BE_L D0-L-PAR D1-L-PAR D2-L-PAR D2_L 108 000 Altera Corporation January 2011 ...
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... Adr D0_L 0 D0_H Adr-PAR D0-L-PAR D0-H-PAR Adr D0_L D1_L D0_H D1_H 7 BE_L BE_H 002 004 008 208 PCI Compiler Version 10.1 Functional Description Figure 3–38 but with the D1_L D2_L D3_L Z D1_H Z D2_H D3_H BE_L Z Z BE_H D2-L-PAR D3-L-PAR D1-L-PAR D2-H-PAR ...
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... Also, because lm_lastn is asserted and lm_rdyn is deasserted in clock cycle 11, the lm_ackn and lm_dxfrn signals remain deasserted after clock cycle 12. 3–116 PCI Compiler User Guide shows the same transaction as in PCI Compiler Version 10.1 Figure 3–38 but with the PCI Altera Corporation January 2011 ...
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... D0-L-PAR Adr-PAR D0-H-PAR Adr D0_L D2_L D1_L D0_H D2_H D1_H 7 BE_L BE_H 004 002 008 208 308 shows a burst memory write master transaction using PCI Compiler Version 10.1 Functional Description D1_L Z D2_L D3_L D1_H D3_H Z D2_H BE_L Z Z BE_H D2-L-PAR D3-L-PAR ...
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... Allow Variable Byte Enables During Burst Transactions turned on and the local side is providing unique byte enables for every data transfer. 3–118 PCI Compiler User Guide Figure 3–38 the local side provides byte enables at the Figure 3–42 the same transaction is shown with PCI Compiler Version 10.1 Altera Corporation January 2011 ...
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... D1_H 7 BE0_L BE1_L BE0_H BE1_H 002 004 008 208 shows a 32-bit single-cycle memory write master transaction. Figure 3–43 3–39, except that the local side master interface transfers only one PCI Compiler Version 10.1 Functional Description D3_L Z D1_L D2_L D3_H Z D1_H D2_H ...
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... Note to Figure 3–43: (1) This signal is not applicable to the pci_mt32 MegaCore function. 3–120 PCI Compiler User Guide Adr 0 7 Adr D0_L 7 BE_L 001 002 004 PCI Compiler Version 10 D0_L Z BE_L Z Adr-PAR D0-L-PAR 008 108 000 Altera Corporation January 2011 ...
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... All 64-bit master transactions are claimed by 64-bit targets that respond with ack64n asserted Perform 64-bit single-cycle master write transactions Initiate 64-bit master write transactions with less initial irdyn latency Figure 3–44 PCI Compiler Version 10.1 Functional Description shows an example of a 64-bit 3–121 ...
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... PCI Compiler User Guide Adr D0_L Adr D0_H 7 BE_L BE_H 001 002 004 PCI Compiler Version 10 D0_L Z D0_H Z BE_L Z Z BE_H D0-L-PAR Adr-PAR D0-H-PAR 008 308 000 Altera Corporation January 2011 ...
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... PCI side first, and the upper 32-bit data word on l_adi[63..32] afterwards. Altera Corporation January 2011 shows the same transaction as in PCI Compiler Version 10.1 Functional Description Figure 3–38, but the PCI 3–123 ...
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... PCI Compiler User Guide Adr D0_L D0_H 0 7 BE_L Adr-PAR D0-L-PAR Adr D0_L D1_L D0_H D1_H 7 BE_L BE_H 002 004 008 Figure PCI Compiler Version 10 D1_L D1_H Z Z D0-H-PAR D1-L-PAR D1-H-PAR 108 000 3–43. This figure applies to Altera Corporation January 2011 ...
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... The PCI specification requires that the master retry the same transaction with the same address at a later time the responsibility of the local-side application to ensure that this requirement is met. PCI Compiler Version 10.1 Functional Description “Disable for more information. for details), they 3–125 ...
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... PCI status register bit 13. Therefore, the signal remains asserted until it is reset by the host. 3–126 PCI Compiler User Guide “Disconnect” on page “Disconnect” on page 3–79. When the pci_mt64 and 3–86. When the pci_mt64 and pci_mt32 PCI Compiler Version 10.1 3–79. When the Altera Corporation January 2011 ...