IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 201

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Host Bridge
Operation
Altera Corporation
January 2011
This section describes using the pci_mt64 and pci_mt32 MegaCore
functions as a host bridge application in a PCI system. The pci_mt64
and pci_mt32 functions support the following advanced master
features, which should be enabled when using the functions in a host
bridge application:
■
■
The host bridge features can be enabled through the Advanced PCI
MegaCore Function Features page of the Parameterize - PCI Compiler
wizard.
Using the PCI MegaCore Function as a Host Bridge
Turning on Use in Host Bridge Application hardwires the master enable
bit of the command register (bit[2]) to a value of 1, which permanently
enables the master functionality of the pci_mt64 and pci_mt32
MegaCore functions. Additionally, the Use in Host Bridge Application
option also allows the pci_mt64 or pci_mt32 master device to generate
configuration read and write transactions to the internal configuration
space. With the Use in Host Bridge Application option, the same logic
and software routines used to access the configuration space of other PCI
devices on the bus can also configure the pci_mt64 or pci_mt32
configuration space.
1
PCI Configuration Read Transaction from the pci_mt64 Local Master
Device to the Internal Configuration Space
Figure 3–46
performing a configuration read transaction from internal configuration
space. The local master requests a 32-bit transaction by asserting the
lm_req32n signal. When requesting a configuration read transaction,
the pci_mt64 function will automatically perform a single-cycle
transaction. The local master signals are asserted as if the pci_mt64
master is completing a single-cycle, 32-bit memory read transaction,
similar to
pci_mt64 function’s internal configuration space will respond to the
transaction without affecting the local side signals.
both the pci_mt64 and pci_mt32 MegaCore functions, excluding the
64-bit extension signals as noted for the pci_mt32 function.
Use in host bridge application
Allow internal arbitration logic
To perform configuration transactions to internal configuration
space, the idsel signal must be connected following the PCI
specification requirements.
Figure 3–44
PCI Compiler Version 10.1
shows the behavior of the pci_mt64 master device
in the Master Mode Operation section. The
Figure 3–46
Functional Description
applies to
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