IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 278
IP-PCI/MT32
Manufacturer Part Number
IP-PCI/MT32
Description
IP CORE - 32-bit 66MHz PCI Master/Target
Manufacturer
Altera
Type
MegaCorer
Datasheet
1.IP-PCIMT32.pdf
(358 pages)
Specifications of IP-PCI/MT32
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone, HardCopy II, MAX II, Stratix
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Compiler, Master/Target, 32 bit
License
Initial License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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Functional Overview
Figure 7–5. PCI-Avalon Bridge Managing the PCI Master/Target Mode with Control Register Access Option
Enabled
7–10
PCI Compiler User Guide
Processor
Master/
Arbiter
Device
Target
Bus
Host
PCI
Bus
PCI
Master/Target Peripheral Mode with Control Register Access Option Enabled
MegaCore
Function
PCI
PCI Host-Bridge Device Mode Operation
Figure 7–6
the connectivity of the PCI Host-Bridge Device mode.
Controller
Controller
Master
Target
PCI
PCI
PCI Compiler Version 10.1
PCI-Avalon Bridge
shows the block diagram of the PCI-Avalon bridge managing
Prefetchable
Prefetchable
Bridge Logic
Registers
Control
Status
Master
Bridge
Bridge
Logic
Logic
Non-
PCI
PCI
Register Access
Avalon Slave
Prefetchable
Avalon Slave
Prefetchable
PCI Bus
Control
Avalon
Acess
Avalon
Master
Master
Non-
Interconnect
System
Fabric
Altera Corporation
January 2011
Peripheral
Peripheral
Peripheral
Peripheral
Master
Master
Slave
Slave
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