IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 174

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Master Mode Operation
Figure 3–33. Burst Memory Read Master Transaction with Local-Side Wait State
Notes to
(1)
(2)
3–100
PCI Compiler User Guide
(1), (2) lm_req64n
This signal is not applicable to the pci_mt32 MegaCore function.
For pci_mt32, lm_req32n should be substituted for lm_req64n for 32-bit master transactions.
(1) l_dato[63..32]
(1) l_cbeni[7..4]
(1) l_hdat_ackn
(1) l_ldat_ackn
(1) ad[63..32]
(1) cben[7..4]
lm_adr_ackn
l_dato[31..0]
l_cbeni[3..0]
lm_tsr[9..0]
l_adi[31..0]
(1) req64n
(1) ack64n
cben[3..0]
Figure
ad[31..0]
(1) par64
lm_dxfrn
lm_lastn
lm_ackn
lm_rdyn
devseln
framen
stopn
trdyn
irdyn
reqn
gntn
par
clk
1
3–33:
000
2
3
Figure 3–33
side inserting a wait state. This figure applies to both the pci_mt64 and
pci_mt32 MegaCore functions, excluding the 64-bit extension signals as
noted for pci_mt32.
001
4
PCI Compiler Version 10.1
5
shows the same transaction as in
Adr
002
0
0
0
0
6
6
BE_H
BE_L
Adr
004
6
7
Adr-PAR
008
Z
Z
8
D0_H
D0_L
208
Z
Z
9
D0-H-PAR
D0-L-PAR
D1_H
BE_H
D1_L
D0_H
BE_L
D0_L
10
308
D1-H-PAR
D1-L-PAR
D1_L
D1_H
D2_L
D2_H
Figure 3–31
11
208
D2-L-PAR
D2-H-PAR
12
D2_H
D2_L
Altera Corporation
308
with the local
13
January 2011
Z
Z
Z
Z
200
14
000