IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 168

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Master Mode Operation
3–94
PCI Compiler User Guide
4.
5.
The pci_mt64 and pci_mt32 functions treat memory read, memory
read multiple, and memory read line commands in the same way. Any
additional requirements for the memory read multiple and memory read
line commands must be implemented by the local-side application.
A turn-around cycle on the ad bus occurs during the clock cycle
immediately following the address phase. During the turn-around
cycle, the PCI side tri-states the ad bus, but drives the correct byte
enables on the cben bus for the first data phase. This process is
necessary because the pci_mt64 function must release the bus so
another PCI agent can drive it.
A PCI target asserts devseln to claim the transaction. One or more
data phases follow, depending on the type of read transaction.
PCI Compiler Version 10.1
Altera Corporation
January 2011