IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 262

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

PCI Configuration
6–12
PCI Compiler User Guide
if the address matches one of the BARs. The PCI-Avalon bridge then
translates the PCI address into an Avalon-MM address before it initiates
the equivalent transaction on the interconnect. The PCI BAR settings in
the PCI Compiler wizard are used to set the appropriate options for the
PCI BAR, so the transactions from PCI can accurately flow to the
interconnect.
For each BAR you must set the following options:
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■
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The following sections explain how to select the appropriate settings for
each option.
BAR Type—The PCI-Avalon bridge supports three BAR types:
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BAR Type
BAR Size
Avalon Base Address
Hardwired PCI Address
32-Bit Prefetchable Memory: This type of BAR is typical for most
systems. It is used for Avalon-MM I/O. Implementing at least one
32-bit prefetchable BAR enables a prefetchable master port for the
PCI-Avalon bridge—except if you select the Single-Cycle Transfers
Only performance profile. This enables both burst and single cycle
access to Avalon-MM peripherals for both read and write
transactions.
You can use this option for all types of Avalon-MM peripherals
except those that do not support prefetchable read transactions.
Peripherals that support prefetchable read transactions do not
modify the state of the data when a read operation is performed. A
RAM or ROM is a typical example of a prefetchable peripheral.
Peripherals where a read operation changes the state of the data,
such as a FIFO buffer or a clear-on read register, are called
non-prefetchable and should not be accessed by a prefetchable base
address register.
64-Bit Prefetchable Memory: This BAR is similar to the 32-bit
prefetchable memory BAR except that it supports 64-bit PCI
addressing. This option is only available if you select 64 Bit PCI Bus
in the System Options - 2 tab. The requirement for your device to
support 64-bit addressing is usually apparent from your system
architecture and is driven by the amount of system memory. Because
the Avalon-MM address space can only support 32-bit addresses,
you are limited to the amount of address space that you can reserve
PCI Compiler Version 10.1
Altera Corporation
January 2011