IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 143

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Figure 3–17. Burst Memory Write Target Transaction with PCI Master Wait State
Note to
(1)
Altera Corporation
January 2011
(1) l_dato[63..32]
(1) l_hdat_ackn
(1) l_beno[7..4]
(1) l_ldat_ackn
This signal is not applicable to the pci_mt32 or pci_t32 MegaCore functions.
(1) ad[63..32]
(1) cben[7..4]
l_adro[31..0]
l_dato[31..0]
l_cmdo[3..0]
l_beno[3..0]
lt_tsr[11..0]
(1) ack64n
(1) req64n
cben[3..0]
lt_framen
ad[31..0]
(1) par64
Figure
devseln
lt_dxfrn
framen
lt_ackn
lt_rdyn
stopn
trdyn
irdyn
par
clk
1
3–17:
2
000
Adr
7
3
Figure 3–17
bus master inserting a wait state. The 64-bit extension signals are not
applicable to the pci_mt32 and pci_t32 functions. The PCI bus master
inserts a wait state by deasserting the irdyn signal in clock cycle 7. The
effect of this wait state on the local side is shown in clock cycle 8 as the
MegaCore function deasserts lt_ackn and as a result lt_dxfrn is also
deasserted. This prevents data from being transferred to the local side in
clock cycle 8 because the internal pipeline of the function does not have
valid data.
Adr-PAR
4
PCI Compiler Version 10.1
D0_H
D0_L
5
shows the same transaction as in
BE0_H
BE0_L
381
D0-H-PAR
D0-L-PAR
6
BE0_H
BE0_L
7
Adr
D0_H
D0_L
7
781
8
BE1_L
BE1_H
D1_H
D1_L
381
9
D1-H-PAR
D1-L-PAR
BE2_L
BE2_H
BE1_L
BE1_H
D2_H
D1_H
D2_L
D1_L
10
D2-H-PAR
D2-L-PAR
BE3_H
BE3_L
BE2_L
BE2_H
D3_L
D3_H
D2_L
D2_H
Figure 3–16
781
11
D3-L-PAR
D3-H-PAR
Functional Description
D3_H
BE3_L
BE3_H
D3_L
12
with the PCI
13
000
14
3–69