IP-PCI/MT32 Altera, IP-PCI/MT32 Datasheet - Page 166

• Manufacturer Part Number: IP-PCI/MT32
• Description: IP CORE - 32-bit 66MHz PCI Master/Target
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IP-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone, HardCopy II, MAX II, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Initial License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Master Mode Operation
3–92
PCI Compiler User Guide
The pci_mt64 and pci_mt32 functions can generate transactions as
specified in
cycles, the function automatically issues a 32-bit single-cycle read/write
transaction.
1
PCI Bus Parking
By asserting the gntn signal of a master device that has not requested bus
access, the PCI bus arbiter may park on any master device when the bus
is idle. In accordance with the PCI Local Bus Specification, Revision 3.0, if
the arbiter parks on pci_mt64 or pci_mt32, the function drives the
ad[31..0], cben[3..0] and par signals.
If the arbiter has parked the bus on pci_mt64 or pci_mt32 and the local
side requests a transaction, the request bit (i.e., lm_tsr[0]) will not be
asserted on the local side. The local state machine will immediately assert
the grant bit (i.e., lm_tsr[1]).
Design Consideration
The arbiter may remove the gntn signal after the local side has asserted
lm_req64n or lm_req32n to request the bus, but before the master
function has been able to assert the framen signal to claim the bus. In this
case, the lm_tsr signals will transition from the grant state (i.e.,
lm_tsr[1] asserted) back to the request state (i.e., lm_tsr[0] asserted)
until the arbiter grants the bus to the requesting function again. In
systems where this situation may occur, the local-side logic should hold
the address and command on the l_adi[31..0] and l_cbeni[3..0]
buses until the address phase bit (i.e., lm_tsr[2]) is asserted to ensure
that the pci_mt64 or pci_mt32 function has assumed mastership of the
bus and that the current address and command have been transferred.
The local-side design may require a long time to transfer data
to/from the function during a burst transaction. The local-side
design must ensure that PCI latency rules are not violated while
the function waits for data. Therefore, the local-side device must
not insert more than eight wait states before asserting lm_rdyn.
PCI Compiler Version 10.1
Table
3–11. When the local side requests I/O or configuration
Altera Corporation
January 2011